Lines Matching refs:And
84 /// and the expression node.
142 /// Utility to insert an atomic instruction based Instrinsic::ID and
213 // Extract boolean success flag and zext it to int.
217 // Extract old value and emit it using the same type as compare value.
241 // did works as if the double-double was stored to memory and then
243 // lower address in both little- and big-Endian modes, but the "load"
348 // Note: Our __builtin_object_size implementation currently treats Type=0 and
395 // LLVM can't handle Type=3 appropriately, and __builtin_object_size shouldn't
401 // LLVM only supports 0 and 2, make sure that we pass along that
426 default: break; // Handle intrinsics and libm functions below.
793 V = Builder.CreateAnd(Eq, IsLessThanInf, "and");
794 V = Builder.CreateAnd(V, IsNormal, "and");
807 V = Builder.CreateAnd(Eq, IsNotInf, "and");
1033 "LLVM's __builtin_eh_return only supports 32- and 64-bit variants");
1052 // register and eventually used as an address, so if the
1053 // addressing registers are wider than pointers and the platform
1152 return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::And, E);
1195 return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::And, E,
1196 llvm::Instruction::And);
1217 llvm::Instruction::And, true);
1271 // to use it with non-atomic loads and stores to get acquire/release
1717 // the result and then compare it to the original result.
1995 // MS builtins via ALL_MS_LANGUAGES and are filtered earlier.
2062 // Unknown builtin, for now just dump it out and return undef.
2132 // FIXME: i128 and f128 doesn't get fully support in Clang and llvm.
2133 // There is a lot of i128 and f128 API missing.
2134 // so we use v16i8 to represent poly128 and get pattern matched.
3362 // currently gives us exactly the same calls for vceqz_f32 and vceqz_s32
3456 // write and register intrinsics only support 32 and 64 bit operations.
3482 // Read into 64 bit register and then truncate result to 32 bit.
3959 // Many NEON builtins have identical semantics and uses in ARM and
4106 // a one-element vector and avoid poor code for i64 in the backend.
5085 // The ARM builtins (and instructions) have the addend as the first
5158 // The ARM builtins (and instructions) have the addend as the first
6171 // Processor features and mapping to processor feature value.
6876 // Emit an intrinsic that has 1 float or double operand, and 1 integer.
7081 // Constant-fold the M4 and M5 mask arguments.
7088 // standard intrinsic. We only support some combinations of M4 and M5.
7213 return MakeBinaryAtomicValue(*this, llvm::AtomicRMWInst::And, E);
