Lines Matching refs:__v8si
52 return (__m256i)__builtin_ia32_pabsd256((__v8si)__a);
64 return (__m256i)__builtin_ia32_packssdw256((__v8si)__a, (__v8si)__b);
76 return (__m256i) __builtin_ia32_packusdw256((__v8si)__V1, (__v8si)__V2);
94 return (__m256i)((__v8si)__a + (__v8si)__b);
197 return (__m256i)((__v8si)__a == (__v8si)__b);
223 return (__m256i)((__v8si)__a > (__v8si)__b);
241 return (__m256i)__builtin_ia32_phaddd256((__v8si)__a, (__v8si)__b);
259 return (__m256i)__builtin_ia32_phsubd256((__v8si)__a, (__v8si)__b);
295 return (__m256i)__builtin_ia32_pmaxsd256((__v8si)__a, (__v8si)__b);
313 return (__m256i)__builtin_ia32_pmaxud256((__v8si)__a, (__v8si)__b);
331 return (__m256i)__builtin_ia32_pminsd256((__v8si)__a, (__v8si)__b);
349 return (__m256i)__builtin_ia32_pminud256((__v8si)__a, (__v8si)__b);
433 return (__m256i)__builtin_ia32_pmuldq256((__v8si)__a, (__v8si)__b);
463 return (__m256i)((__v8si)__a * (__v8si)__b);
469 return __builtin_ia32_pmuludq256((__v8si)__a, (__v8si)__b);
491 (__m256i)__builtin_shufflevector((__v8si)(__m256i)(a), \
492 (__v8si)_mm256_setzero_si256(), \
541 return (__m256i)__builtin_ia32_psignd256((__v8si)__a, (__v8si)__b);
564 return (__m256i)__builtin_ia32_pslldi256((__v8si)__a, __count);
570 return (__m256i)__builtin_ia32_pslld256((__v8si)__a, (__v4si)__count);
600 return (__m256i)__builtin_ia32_psradi256((__v8si)__a, __count);
606 return (__m256i)__builtin_ia32_psrad256((__v8si)__a, (__v4si)__count);
629 return (__m256i)__builtin_ia32_psrldi256((__v8si)__a, __count);
635 return (__m256i)__builtin_ia32_psrld256((__v8si)__a, (__v4si)__count);
665 return (__m256i)((__v8si)__a - (__v8si)__b);
713 return (__m256i)__builtin_shufflevector((__v8si)__a, (__v8si)__b, 2, 8+2, 3, 8+3, 6, 8+6, 7, 8+7);
737 return (__m256i)__builtin_shufflevector((__v8si)__a, (__v8si)__b, 0, 8+0, 1, 8+1, 4, 8+4, 5, 8+5);
797 (__m256i)__builtin_shufflevector((__v8si)(__m256i)(V1), \
798 (__v8si)(__m256i)(V2), \
860 return (__m256i)__builtin_ia32_permvarsi256((__v8si)__a, (__v8si)__b);
872 return (__m256)__builtin_ia32_permvarsf256((__v8sf)__a, (__v8si)__b);
901 return (__m256i)__builtin_ia32_maskloadd256((const __v8si *)__X, (__v8si)__M);
925 __builtin_ia32_maskstored256((__v8si *)__X, (__v8si)__M, (__v8si)__Y);
949 return (__m256i)__builtin_ia32_psllv8si((__v8si)__X, (__v8si)__Y);
973 return (__m256i)__builtin_ia32_psrav8si((__v8si)__X, (__v8si)__Y);
985 return (__m256i)__builtin_ia32_psrlv8si((__v8si)__X, (__v8si)__Y);
1039 (__v8si)(__m256i)(i), \
1061 (__m256i)__builtin_ia32_gatherd_d256((__v8si)(__m256i)(a), \
1063 (__v8si)(__m256i)(i), \
1064 (__v8si)(__m256i)(mask), (s)); })
1147 (__v8si)(__m256i)(i), \
1175 (__m256i)__builtin_ia32_gatherd_d256((__v8si)_mm256_undefined_si256(), \
1176 (int const *)(m), (__v8si)(__m256i)(i), \
1177 (__v8si)_mm256_set1_epi32(-1), (s)); })
