Lines Matching full:surf
91 struct radeon_surface *surf);
93 struct radeon_surface *surf);
162 static void surf_minify(struct radeon_surface *surf,
168 surflevel->npix_x = mip_minify(surf->npix_x, level);
169 surflevel->npix_y = mip_minify(surf->npix_y, level);
170 surflevel->npix_z = mip_minify(surf->npix_z, level);
171 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
172 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
173 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
174 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
175 !(surf->flags & RADEON_SURF_FMASK)) {
186 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
189 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
262 struct radeon_surface *surf,
270 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
278 if (surf->flags & RADEON_SURF_SCANOUT) {
279 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
283 for (i = start_level; i <= surf->last_level; i++) {
284 surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
285 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
287 offset = surf->bo_size;
289 offset = ALIGN(offset, surf->bo_alignment);
296 struct radeon_surface *surf,
304 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
311 for (i = start_level; i <= surf->last_level; i++) {
312 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
313 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
315 offset = surf->bo_size;
317 offset = ALIGN(offset, surf->bo_alignment);
324 struct radeon_surface *surf,
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
336 if (surf->flags & RADEON_SURF_SCANOUT) {
337 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
340 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
344 for (i = start_level; i <= surf->last_level; i++) {
345 surf->level[i].mode = RADEON_SURF_MODE_1D;
346 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
348 offset = surf->bo_size;
350 offset = ALIGN(offset, surf->bo_alignment);
357 struct radeon_surface *surf,
367 (tilew * surf->bpe * surf->nsamples);
369 if (surf->flags & RADEON_SURF_FMASK)
372 if (surf->flags & RADEON_SURF_SCANOUT) {
373 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
376 surf->bo_alignment =
379 surf->nsamples * surf->bpe * 64,
380 xalign * yalign * surf->nsamples * surf->bpe);
384 for (i = start_level; i <= surf->last_level; i++) {
385 surf->level[i].mode = RADEON_SURF_MODE_2D;
386 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
387 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
388 return r6_surface_init_1d(surf_man, surf, offset, i);
391 offset = surf->bo_size;
393 offset = ALIGN(offset, surf->bo_alignment);
400 struct radeon_surface *surf)
406 if (surf->nsamples > 1) {
407 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
408 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
412 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
414 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
422 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
423 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
430 if (surf->nsamples > 1) {
435 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
436 surf->flags |= RADEON_SURF_SET(mode, MODE);
440 if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) {
445 if (surf->last_level > 14) {
452 r = r6_surface_init_linear(surf_man, surf, 0, 0);
455 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
458 r = r6_surface_init_1d(surf_man, surf, 0, 0);
461 r = r6_surface_init_2d(surf_man, surf, 0, 0);
470 struct radeon_surface *surf)
565 static void eg_surf_minify(struct radeon_surface *surf,
577 surflevel->npix_x = mip_minify(surf->npix_x, level);
578 surflevel->npix_y = mip_minify(surf->npix_y, level);
579 surflevel->npix_z = mip_minify(surf->npix_z, level);
580 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
581 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
582 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
583 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
584 !(surf->flags & RADEON_SURF_FMASK)) {
600 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
603 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
607 struct radeon_surface *surf,
617 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples);
621 if (surf->flags & RADEON_SURF_SCANOUT) {
627 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
635 for (i = start_level; i <= surf->last_level; i++) {
637 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
639 offset = surf->bo_size;
641 offset = ALIGN(offset, surf->bo_alignment);
648 struct radeon_surface *surf,
661 tileb = tilew * tileh * bpe * surf->nsamples;
670 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
671 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
677 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
685 for (i = start_level; i <= surf->last_level; i++) {
687 eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset);
689 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
692 offset = surf->bo_size;
694 offset = ALIGN(offset, surf->bo_alignment);
701 struct radeon_surface *surf,
707 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
712 if (surf->last_level > 15) {
718 if (surf->nsamples > 1) {
723 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
724 surf->flags |= RADEON_SURF_SET(mode, MODE);
729 switch (surf->tile_split) {
741 switch (surf->mtilea) {
751 if (surf_man->hw_info.num_banks < surf->mtilea) {
755 switch (surf->bankw) {
765 switch (surf->bankh) {
774 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
775 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
784 struct radeon_surface *surf)
787 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
791 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp;
793 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
798 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1,
799 surf->bo_size, 0);
800 surf->stencil_offset = stencil_level[0].offset;
806 struct radeon_surface *surf)
809 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
813 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp;
815 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
816 surf->tile_split, 0, 0);
821 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1,
822 surf->stencil_tile_split, surf->bo_size, 0);
823 surf->stencil_offset = stencil_level[0].offset;
829 struct radeon_surface *surf)
835 if (surf->nsamples > 1) {
836 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
837 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
841 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
843 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
851 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
852 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
857 r = eg_surface_sanity(surf_man, surf, mode);
862 surf->stencil_offset = 0;
863 surf->bo_alignment = 0;
868 r = r6_surface_init_linear(surf_man, surf, 0, 0);
871 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
874 r = eg_surface_init_1d_miptrees(surf_man, surf);
877 r = eg_surface_init_2d_miptrees(surf_man, surf);
904 struct radeon_surface *surf)
910 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
913 surf->tile_split = 1024;
914 surf->bankw = 1;
915 surf->bankh = 1;
916 surf->mtilea = surf_man->hw_info.num_banks;
917 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
918 for (; surf->bankh <= 8; surf->bankh *= 2) {
919 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
923 if (surf->mtilea > 8) {
924 surf->mtilea = 8;
927 r = eg_surface_sanity(surf_man, surf, mode);
938 if (surf->nsamples > 1) {
939 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
940 switch (surf->nsamples) {
942 surf->tile_split = 128;
945 surf->tile_split = 128;
948 surf->tile_split = 256;
951 surf->tile_split = 512;
955 surf->nsamples, __LINE__);
958 surf->stencil_tile_split = 64;
961 surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
962 if (surf->tile_split > 4096)
963 surf->tile_split = 4096;
967 surf->tile_split = surf_man->hw_info.row_size;
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
979 if (surf->flags & RADEON_SURF_SBUFFER) {
983 tileb = MIN2(surf->tile_split, 64 * surf->nsamples);
985 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
991 surf->bankw = 1;
994 surf->bankh = 4;
998 surf->bankh = 2;
1001 surf->bankh = 1;
1005 for (; surf->bankh <= 8; surf->bankh *= 2) {
1006 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
1011 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
1012 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
1013 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
1280 struct radeon_surface *surf,
1286 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
1291 if (surf->last_level > 15) {
1297 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
1298 if (surf->nsamples > 1) {
1303 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1304 surf->flags |= RADEON_SURF_SET(mode, MODE);
1307 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
1311 if (!surf->tile_split) {
1313 surf->mtilea = 1;
1314 surf->bankw = 1;
1315 surf->bankh = 1;
1316 surf->tile_split = 64;
1317 surf->stencil_tile_split = 64;
1322 if (surf->flags & RADEON_SURF_SBUFFER) {
1323 switch (surf->nsamples) {
1341 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split);
1343 if (surf->flags & RADEON_SURF_ZBUFFER) {
1344 switch (surf->nsamples) {
1360 } else if (surf->flags & RADEON_SURF_SCANOUT) {
1361 switch (surf->bpe) {
1372 switch (surf->bpe) {
1392 si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_split);
1395 if (surf->flags & RADEON_SURF_SBUFFER) {
1398 if (surf->flags & RADEON_SURF_ZBUFFER) {
1400 } else if (surf->flags & RADEON_SURF_SCANOUT) {
1414 static void si_surf_minify(struct radeon_surface *surf,
1421 surflevel->npix_x = surf->npix_x;
1423 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
1425 surflevel->npix_y = mip_minify(surf->npix_y, level);
1426 surflevel->npix_z = mip_minify(surf->npix_z, level);
1428 if (level == 0 && surf->last_level > 0) {
1429 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;
1430 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;
1431 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;
1433 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
1434 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
1435 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
1443 if (level == 0 && surf->last_level == 0)
1445 /* Using just bpe here breaks stencil blitting; surf->bpe works. */
1446 xalign = MAX2(xalign, slice_align / surf->bpe);
1455 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
1459 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1462 static void si_surf_minify_2d(struct radeon_surface *surf,
1471 surflevel->npix_x = surf->npix_x;
1473 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
1475 surflevel->npix_y = mip_minify(surf->npix_y, level);
1476 surflevel->npix_z = mip_minify(surf->npix_z, level);
1478 if (level == 0 && surf->last_level > 0) {
1479 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;
1480 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;
1481 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;
1483 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
1484 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
1485 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
1488 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
1489 !(surf->flags & RADEON_SURF_FMASK)) {
1504 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
1507 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1511 struct radeon_surface *surf,
1520 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
1522 xalign = MAX2(8, 64 / surf->bpe);
1525 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes);
1528 surf->last_level; i++) {
1529 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1530 si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset);
1532 offset = surf->bo_size;
1534 offset = ALIGN(offset, surf->bo_alignment);
1536 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
1537 surf->tiling_index[i] = tile_mode;
1544 struct radeon_surface *surf,
1558 if (surf->flags & RADEON_SURF_SCANOUT) {
1563 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
1571 for (i = start_level; i <= surf->last_level; i++) {
1573 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset);
1575 offset = surf->bo_size;
1579 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
1580 if (surf->level == level) {
1581 surf->tiling_index[i] = tile_mode;
1583 surf->stencil_tiling_index[i] = tile_mode;
1585 surf->stencil_tiling_index[i] = tile_mode;
1593 struct radeon_surface *surf,
1598 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1603 if (surf->flags & RADEON_SURF_SBUFFER) {
1604 r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0);
1605 surf->stencil_offset = surf->stencil_level[0].offset;
1611 struct radeon_surface *surf,
1628 tileb = tilew * tileh * bpe * surf->nsamples;
1637 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea;
1638 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea;
1645 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
1653 for (i = start_level; i <= surf->last_level; i++) {
1655 si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
1674 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1677 aligned_offset = offset = surf->bo_size;
1679 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
1681 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
1682 if (surf->level == level) {
1683 surf->tiling_index[i] = tile_mode;
1685 surf->stencil_tiling_index[i] = tile_mode;
1687 surf->stencil_tiling_index[i] = tile_mode;
1695 struct radeon_surface *surf,
1706 r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
1711 if (surf->flags & RADEON_SURF_SBUFFER) {
1712 r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, surf->stencil_tile_split, surf->bo_size, 0);
1713 surf->stencil_offset = surf->stencil_level[0].offset;
1719 struct radeon_surface *surf)
1725 if (surf->nsamples > 1) {
1726 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1727 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
1731 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
1733 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
1741 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1742 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1747 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1752 surf->stencil_offset = 0;
1753 surf->bo_alignment = 0;
1758 r = r6_surface_init_linear(surf_man, surf, 0, 0);
1761 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
1764 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1767 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1779 struct radeon_surface *surf)
1784 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
1786 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) &&
1787 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) {
1789 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1790 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1793 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2110 struct radeon_surface *surf,
2114 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
2119 if (surf->last_level > 15) {
2125 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
2126 if (surf->nsamples > 1) {
2131 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2132 surf->flags |= RADEON_SURF_SET(mode, MODE);
2135 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
2139 if (!surf->tile_split) {
2141 surf->mtilea = 1;
2142 surf->bankw = 1;
2143 surf->bankh = 1;
2144 surf->tile_split = 64;
2145 surf->stencil_tile_split = 64;
2150 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) {
2151 switch (surf->nsamples) {
2166 if (surf->flags & RADEON_SURF_SBUFFER) {
2169 cik_get_2d_params(surf_man, 1, surf->nsamples, false,
2171 &surf->stencil_tile_split,
2174 } else if (surf->flags & RADEON_SURF_SCANOUT) {
2181 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2182 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode,
2183 NULL, &surf->tile_split, NULL, &surf->mtilea,
2184 &surf->bankw, &surf->bankh);
2188 if (surf->flags & RADEON_SURF_SBUFFER) {
2191 if (surf->flags & RADEON_SURF_ZBUFFER) {
2193 } else if (surf->flags & RADEON_SURF_SCANOUT) {
2208 struct radeon_surface *surf,
2229 tileb = surf->nsamples * tileb_1x;
2239 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea;
2240 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea;
2247 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
2255 for (i = start_level; i <= surf->last_level; i++) {
2257 si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
2276 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2279 aligned_offset = offset = surf->bo_size;
2281 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
2283 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
2284 if (surf->level == level) {
2285 surf->tiling_index[i] = tile_mode;
2287 surf->stencil_tiling_index[i] = tile_mode;
2289 surf->stencil_tiling_index[i] = tile_mode;
2297 struct radeon_surface *surf,
2303 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2304 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode,
2307 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,
2308 surf->tile_split, num_pipes, num_banks, 0, 0);
2313 if (surf->flags & RADEON_SURF_SBUFFER) {
2314 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode,
2315 surf->stencil_tile_split, num_pipes, num_banks,
2316 surf->bo_size, 0);
2317 surf->stencil_offset = surf->stencil_level[0].offset;
2323 struct radeon_surface *surf)
2329 if (surf->nsamples > 1) {
2330 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2331 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
2335 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
2337 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
2345 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2346 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
2351 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2356 surf->stencil_offset = 0;
2357 surf->bo_alignment = 0;
2362 r = r6_surface_init_linear(surf_man, surf, 0, 0);
2365 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
2368 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2371 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2383 struct radeon_surface *surf)
2388 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
2390 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) &&
2391 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) {
2393 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2394 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
2397 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2460 struct radeon_surface *surf,
2464 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) {
2469 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) {
2472 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) {
2475 if (!surf->array_size) {
2479 surf->array_size = next_power_of_two(surf->array_size);
2481 switch (surf->nsamples) {
2493 if (surf->npix_y > 1) {
2497 if (surf->npix_z > 1) {
2502 if (surf->npix_z > 1) {
2507 surf->array_size = 8;
2509 surf->array_size = 6;
2515 if (surf->npix_y > 1) {
2528 struct radeon_surface *surf)
2533 type = RADEON_SURF_GET(surf->flags, TYPE);
2534 mode = RADEON_SURF_GET(surf->flags, MODE);
2536 r = radeon_surface_sanity(surf_man, surf, type, mode);
2540 return surf_man->surface_init(surf_man, surf);
2545 struct radeon_surface *surf)
2550 type = RADEON_SURF_GET(surf->flags, TYPE);
2551 mode = RADEON_SURF_GET(surf->flags, MODE);
2553 r = radeon_surface_sanity(surf_man, surf, type, mode);
2557 return surf_man->surface_best(surf_man, surf);
