Lines Matching refs:tile_mode
1281 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
1346 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D;
1349 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA;
1352 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA;
1355 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA;
1363 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1366 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1374 *tile_mode = SI_TILE_MODE_COLOR_2D_8BPP;
1377 *tile_mode = SI_TILE_MODE_COLOR_2D_16BPP;
1380 *tile_mode = SI_TILE_MODE_COLOR_2D_32BPP;
1384 *tile_mode = SI_TILE_MODE_COLOR_2D_64BPP;
1391 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
1399 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
1401 *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
1403 *tile_mode = SI_TILE_MODE_COLOR_1D;
1408 *tile_mode = SI_TILE_MODE_COLOR_LINEAR_ALIGNED;
1512 unsigned tile_mode,
1537 surf->tiling_index[i] = tile_mode;
1546 unsigned bpe, unsigned tile_mode,
1581 surf->tiling_index[i] = tile_mode;
1583 surf->stencil_tiling_index[i] = tile_mode;
1585 surf->stencil_tiling_index[i] = tile_mode;
1594 unsigned tile_mode, unsigned stencil_tile_mode)
1598 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1613 unsigned bpe, unsigned tile_mode,
1657 switch (tile_mode) {
1662 tile_mode = SI_TILE_MODE_COLOR_1D;
1666 tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
1669 tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
1674 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1683 surf->tiling_index[i] = tile_mode;
1685 surf->stencil_tiling_index[i] = tile_mode;
1687 surf->stencil_tiling_index[i] = tile_mode;
1696 unsigned tile_mode, unsigned stencil_tile_mode)
1703 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1706 r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
1721 unsigned mode, tile_mode, stencil_tile_mode;
1747 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1761 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
1764 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1767 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1781 unsigned mode, tile_mode, stencil_tile_mode;
1793 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1852 unsigned tile_mode,
1860 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
2111 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
2153 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64;
2157 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128;
2160 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256;
2167 *stencil_tile_mode = *tile_mode;
2175 *tile_mode = CIK_TILE_MODE_COLOR_2D_SCANOUT;
2177 *tile_mode = CIK_TILE_MODE_COLOR_2D;
2182 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode,
2192 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
2194 *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
2196 *tile_mode = SI_TILE_MODE_COLOR_1D;
2201 *tile_mode = SI_TILE_MODE_COLOR_LINEAR_ALIGNED;
2210 unsigned bpe, unsigned tile_mode,
2259 switch (tile_mode) {
2261 tile_mode = SI_TILE_MODE_COLOR_1D;
2264 tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
2271 tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
2276 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2285 surf->tiling_index[i] = tile_mode;
2287 surf->stencil_tiling_index[i] = tile_mode;
2289 surf->stencil_tiling_index[i] = tile_mode;
2298 unsigned tile_mode, unsigned stencil_tile_mode)
2304 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode,
2307 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,
2325 unsigned mode, tile_mode, stencil_tile_mode;
2351 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2365 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
2368 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2371 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2385 unsigned mode, tile_mode, stencil_tile_mode;
2397 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
