Lines Matching refs:v14
272 smull v14.4s, v10.4h, v0.h[0]
273 smlal v14.4s, v11.4h, v1.h[2]
299 smlal v14.4s, v4.4h, v3.h[0]
300 smlsl v14.4s, v5.4h, v3.h[2]
366 smlsl v14.4s, v10.4h, v0.h[0]
367 smlsl v14.4s, v11.4h, v0.h[2]
368 smlsl v14.4s, v4.4h, v1.h[0]
369 smlsl v14.4s, v5.4h, v2.h[2]
387 add v12.4s, v14.4s , v26.4s
388 sub v24.4s, v14.4s , v26.4s
390 add v14.4s, v16.4s , v28.4s
405 sqrshrn v31.4h, v14.4s,#shift_stage1_idct //// x2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
410 sqrshrn v14.4h, v28.4s,#shift_stage1_idct //// x4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
647 trn1 v26.4h, v14.4h, v8.4h
648 trn2 v27.4h, v14.4h, v8.4h
652 trn1 v14.2s, v26.2s, v28.2s
690 st1 { v14.4h, v15.4h},[x1],#16
771 smull v14.4s, v10.4h, v0.h[0]
772 smlal v14.4s, v11.4h, v1.h[2]
794 smlal v14.4s, v4.4h, v3.h[0]
795 smlsl v14.4s, v5.4h, v3.h[2]
850 smlsl v14.4s, v10.4h, v0.h[0]
851 smlsl v14.4s, v11.4h, v0.h[2]
852 smlsl v14.4s, v4.4h, v1.h[0]
853 smlsl v14.4s, v5.4h, v2.h[2]
879 add v12.4s, v14.4s , v26.4s
880 sub v24.4s, v14.4s , v26.4s
882 add v14.4s, v16.4s , v28.4s
897 sqrshrn v31.4h, v14.4s,#shift_stage2_idct //// x2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
902 sqrshrn v14.4h, v28.4s,#shift_stage2_idct //// x4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
1113 trn1 v26.4h, v14.4h, v8.4h
1114 trn2 v27.4h, v14.4h, v8.4h
1118 trn1 v14.2s, v26.2s, v28.2s
1152 // swapping v23 and v14
1154 mov v23.d[0],v14.d[0]
1155 mov v14.d[0],v23.d[1]
1188 mov v14.d[1] ,v15.d[0]
1197 uaddw v14.8h, v14.8h , v25.8b
1207 sqxtun v25.8b, v14.8h
