Lines Matching refs:in1
262 Arguments : Inputs - in0, in1, in2, in3, pdst, stride
264 Store word from 'in1' to (pdst + stride)
268 #define SW4(in0, in1, in2, in3, pdst, stride) { \
270 SW(in1, (pdst) + stride); \
276 Arguments : Inputs - in0, in1, in2, in3, pdst, stride
278 Store double word from 'in1' to (pdst + stride)
282 #define SD4(in0, in1, in2, in3, pdst, stride) { \
284 SD(in1, (pdst) + stride); \
396 Arguments : Inputs - in0, in1, pdst, stride
398 Store 16 byte elements from 'in1' to (pdst + stride)
400 #define ST_B2(RTYPE, in0, in1, pdst, stride) { \
402 ST_B(RTYPE, in1, (pdst) + stride); \
406 #define ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride) { \
407 ST_B2(RTYPE, in0, in1, (pdst), stride); \
412 #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
414 ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride); \
420 Arguments : Inputs - in0, in1, pdst, stride
422 Store 8 halfword elements from 'in1' to (pdst + stride)
424 #define ST_H2(RTYPE, in0, in1, pdst, stride) { \
426 ST_H(RTYPE, in1, (pdst) + stride); \
430 #define ST_H4(RTYPE, in0, in1, in2, in3, pdst, stride) { \
431 ST_H2(RTYPE, in0, in1, (pdst), stride); \
436 #define ST_H8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) { \
437 ST_H4(RTYPE, in0, in1, in2, in3, (pdst), stride); \
443 Arguments : Inputs - in0, in1, pdst, stride
445 Store 4 word elements from 'in1' to (pdst + stride)
447 #define ST_SW2(in0, in1, pdst, stride) { \
449 ST_SW(in1, (pdst) + stride); \
497 Arguments : Inputs - in0, in1, pdst, stride
507 #define ST4x4_UB(in0, in1, idx0, idx1, idx2, idx3, pdst, stride) { \
513 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \
514 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \
518 #define ST4x8_UB(in0, in1, pdst, stride) { \
522 ST4x4_UB(in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride); \
557 Arguments : Inputs - in0, in1, pdst, stride
562 Index 0 double word element from 'in1' vector is copied to the
564 Index 1 double word element from 'in1' vector is copied to the
567 #define ST8x4_UB(in0, in1, pdst, stride) { \
573 out2_m = __msa_copy_u_d((v2i64)in1, 0); \
574 out3_m = __msa_copy_u_d((v2i64)in1, 1); \
579 /* Description : average with rounding (in0 + in1 + 1) / 2.
580 Arguments : Inputs - in0, in1, in2, in3,
584 each unsigned byte element from 'in1' vector. Then the average
587 #define AVER_UB2(RTYPE, in0, in1, in2, in3, out0, out1) { \
588 out0 = (RTYPE)__msa_aver_u_b((v16u8)in0, (v16u8)in1); \
593 #define AVER_UB4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
595 AVER_UB2(RTYPE, in0, in1, in2, in3, out0, out1) \
601 Arguments : Inputs - in0, in1, slide_val
607 #define SLDI_B2_0(RTYPE, in0, in1, out0, out1, slide_val) { \
610 out1 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in1, slide_val); \
614 #define SLDI_B4_0(RTYPE, in0, in1, in2, in3, \
616 SLDI_B2_0(RTYPE, in0, in1, out0, out1, slide_val); \
644 Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
647 Details : Byte elements from 'in0' & 'in1' are copied selectively to
650 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \
651 out0 = (RTYPE)__msa_vshf_b((v16i8)mask0, (v16i8)in1, (v16i8)in0); \
658 #define VSHF_B4(RTYPE, in0, in1, mask0, mask1, mask2, mask3, \
660 VSHF_B2(RTYPE, in0, in1, in0, in1, mask0, mask1, out0, out1); \
661 VSHF_B2(RTYPE, in0, in1, in0, in1, mask2, mask3, out2, out3); \
810 Arguments : Inputs - in0, in1, min_vec
816 #define MIN_UH2(RTYPE, in0, in1, min_vec) { \
818 in1 = (RTYPE)__msa_min_u_h((v8u16)in1, min_vec); \
822 #define MIN_UH4(RTYPE, in0, in1, in2, in3, min_vec) { \
823 MIN_UH2(RTYPE, in0, in1, min_vec); \
842 #define CLIP_SH2_0_255(in0, in1) { \
844 in1 = CLIP_SH_0_255(in1); \
846 #define CLIP_SH4_0_255(in0, in1, in2, in3) { \
847 CLIP_SH2_0_255(in0, in1); \
890 Arguments : Inputs - in0, in1
897 #define HADD_UB2(RTYPE, in0, in1, out0, out1) { \
899 out1 = (RTYPE)__msa_hadd_u_h((v16u8)in1, (v16u8)in1); \
903 #define HADD_UB4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3) { \
904 HADD_UB2(RTYPE, in0, in1, out0, out1); \
910 Arguments : Inputs - in0, in1
917 #define HSUB_UB2(RTYPE, in0, in1, out0, out1) { \
919 out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1); \
924 Arguments : Inputs - in0, in1, ref0, ref1
931 #define SAD_UB2_UH(in0, in1, ref0, ref1) ({ \
936 diff1_m = __msa_asub_u_b((v16u8)in1, (v16u8)ref1); \
945 Arguments : Inputs - in0, in1
952 #define HSUB_UH2(RTYPE, in0, in1, out0, out1) { \
954 out1 = (RTYPE)__msa_hsub_s_w((v8i16)in1, (v8i16)in1); \
959 Arguments : Inputs - in0, in1, in2, in3
964 #define INSERT_W2(RTYPE, in0, in1, out) { \
966 out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
970 #define INSERT_W4(RTYPE, in0, in1, in2, in3, out) { \
972 out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
979 #define INSERT_D2(RTYPE, in0, in1, out) { \
981 out = (RTYPE)__msa_insert_d((v2i64)out, 1, in1); \
987 Arguments : Inputs - in0, in1, in2, in3
990 Details : Even byte elements of 'in0' and 'in1' are interleaved
993 #define ILVEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) { \
994 out0 = (RTYPE)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \
1001 Arguments : Inputs - in0, in1, in2, in3
1004 Details : Even halfword elements of 'in0' and 'in1' are interleaved
1007 #define ILVEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1008 out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0); \
1016 Arguments : Inputs - in0, in1, in2, in3
1019 Details : Even word elements of 'in0' and 'in1' are interleaved
1022 #define ILVEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1023 out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \
1029 Arguments : Inputs - in0, in1, in2, in3
1032 Details : Even double word elements of 'in0' and 'in1' are interleaved
1035 #define ILVEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1036 out0 = (RTYPE)__msa_ilvev_d((v2i64)in1, (v2i64)in0); \
1042 Arguments : Inputs - in0, in1, in2, in3
1045 Details : Left half of byte elements of 'in0' and 'in1' are interleaved
1048 #define ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1049 out0 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
1057 #define ILVL_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1059 ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
1066 Arguments : Inputs - in0, in1, in2, in3
1069 Details : Left half of halfword elements of 'in0' and 'in1' are
1072 #define ILVL_H2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1073 out0 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \
1079 Arguments : Inputs - in0, in1, in2, in3
1082 Details : Left half of word elements of 'in0' and 'in1' are interleaved
1085 #define ILVL_W2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1086 in1); \
1093 Arguments : Inputs - in0, in1, in2, in3
1096 Details : Right half of byte elements of 'in0' and 'in1' are interleaved
1099 #define ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1100 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
1108 #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1110 ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
1118 #define ILVR_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1121 ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1129 Arguments : Inputs - in0, in1, in2, in3
1132 Details : Right half of halfword elements of 'in0' and 'in1' are
1135 #define ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1136 out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
1141 #define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1143 ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1); \
1148 #define ILVR_W2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1149 out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
1155 #define ILVR_W4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1157 ILVR_W2(RTYPE, in0, in1, in2, in3, out0, out1); \
1163 Arguments : Inputs - in0, in1, in2, in3
1166 Details : Right half of double word elements of 'in0' and 'in1' are
1169 #define ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1170 out0 = (RTYPE)__msa_ilvr_d((v2i64)(in0), (v2i64)(in1)); \
1177 #define ILVR_D3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2) { \
1178 ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
1183 #define ILVR_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1185 ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
1192 Arguments : Inputs - in0, in1
1195 Details : Right half of byte elements from 'in0' and 'in1' are
1198 #define ILVRL_B2(RTYPE, in0, in1, out0, out1) { \
1199 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
1200 out1 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
1207 #define ILVRL_H2(RTYPE, in0, in1, out0, out1) { \
1208 out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
1209 out1 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \
1214 #define ILVRL_W2(RTYPE, in0, in1, out0, out1) { \
1215 out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
1216 out1 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \
1224 Arguments : Inputs - in0, in1, sat_val
1231 #define SAT_UH2(RTYPE, in0, in1, sat_val) { \
1233 in1 = (RTYPE)__msa_sat_u_h((v8u16)in1, sat_val); \
1237 #define SAT_UH4(RTYPE, in0, in1, in2, in3, sat_val) { \
1238 SAT_UH2(RTYPE, in0, in1, sat_val); \
1246 Arguments : Inputs - in0, in1, sat_val
1253 #define SAT_SH2(RTYPE, in0, in1, sat_val) { \
1255 in1 = (RTYPE)__msa_sat_s_h((v8i16)in1, sat_val); \
1259 #define SAT_SH4(RTYPE, in0, in1, in2, in3, sat_val) { \
1260 SAT_SH2(RTYPE, in0, in1, sat_val); \
1289 Arguments : Inputs - in0, in1, in2, in3
1293 'out0' & even byte elements of 'in1' are copied to the right
1296 #define PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1297 out0 = (RTYPE)__msa_pckev_b((v16i8)in0, (v16i8)in1); \
1304 #define PCKEV_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1306 PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
1314 Arguments : Inputs - in0, in1, in2, in3
1318 'out0' & even halfword elements of 'in1' are copied to the
1321 #define PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1322 out0 = (RTYPE)__msa_pckev_h((v8i16)in0, (v8i16)in1); \
1328 #define PCKEV_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1330 PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1); \
1336 Arguments : Inputs - in0, in1, in2, in3
1340 'out0' & even double elements of 'in1' are copied to the right
1343 #define PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1344 out0 = (RTYPE)__msa_pckev_d((v2i64)in0, (v2i64)in1); \
1350 #define PCKEV_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1352 PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
1358 Arguments : Inputs - in0, in1
1364 #define XORI_B2_128(RTYPE, in0, in1) { \
1366 in1 = (RTYPE)__msa_xori_b((v16u8)in1, 128); \
1371 #define XORI_B3_128(RTYPE, in0, in1, in2) { \
1372 XORI_B2_128(RTYPE, in0, in1); \
1377 #define XORI_B4_128(RTYPE, in0, in1, in2, in3) { \
1378 XORI_B2_128(RTYPE, in0, in1); \
1384 #define XORI_B7_128(RTYPE, in0, in1, in2, in3, in4, in5, in6) { \
1385 XORI_B4_128(RTYPE, in0, in1, in2, in3); \
1391 Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
1395 signed halfword element of 'in1' with full precision resulting
1399 #define AVE_SH4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1401 out0 = (RTYPE)__msa_ave_s_h((v8i16)in0, (v8i16)in1); \
1409 Arguments : Inputs - in0, in1, in2, in3
1413 halfword elements of 'in1'. The result is then signed saturated
1416 #define ADDS_SH2(RTYPE, in0, in1, in2, in3, out0, out1) { \
1417 out0 = (RTYPE)__msa_adds_s_h((v8i16)in0, (v8i16)in1); \
1422 #define ADDS_SH4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1424 ADDS_SH2(RTYPE, in0, in1, in2, in3, out0, out1); \
1430 Arguments : Inputs - in0, in1, in2, in3, shift
1436 #define SLLI_4V(in0, in1, in2, in3, shift) { \
1438 in1 = in1 << shift; \
1445 Arguments : Inputs - in0, in1, in2, in3, shift
1451 #define SRA_4V(in0, in1, in2, in3, shift) { \
1453 in1 = in1 >> shift; \
1459 Arguments : Inputs - in0, in1, shift
1468 #define SRAR_W2(RTYPE, in0, in1, shift) { \
1470 in1 = (RTYPE)__msa_srar_w((v4i32)in1, (v4i32)shift); \
1473 #define SRAR_W4(RTYPE, in0, in1, in2, in3, shift) { \
1474 SRAR_W2(RTYPE, in0, in1, shift) \
1480 Arguments : Inputs - in0, in1, shift
1488 #define SRARI_H2(RTYPE, in0, in1, shift) { \
1490 in1 = (RTYPE)__msa_srari_h((v8i16)in1, shift); \
1495 #define SRARI_H4(RTYPE, in0, in1, in2, in3, shift) { \
1496 SRARI_H2(RTYPE, in0, in1, shift); \
1502 #define SRARI_W2(RTYPE, in0, in1, shift) { \
1504 in1 = (RTYPE)__msa_srari_w((v4i32)in1, shift); \
1508 #define SRARI_W4(RTYPE, in0, in1, in2, in3, shift) { \
1509 SRARI_W2(RTYPE, in0, in1, shift); \
1515 Arguments : Inputs - in0, in1, in2, in3, shift
1521 #define SRLI_H4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3, shift) { \
1523 out1 = (RTYPE)__msa_srli_h((v8i16)in1, shift); \
1530 Arguments : Inputs - in0, in1, in2, in3
1532 Details : Each element from 'in0' is multiplied with elements from 'in1'
1535 #define MUL2(in0, in1, in2, in3, out0, out1) { \
1536 out0 = in0 * in1; \
1539 #define MUL4(in0, in1, in2, in3, in4, in5, in6, in7, \
1541 MUL2(in0, in1, in2, in3, out0, out1); \
1546 Arguments : Inputs - in0, in1, in2, in3
1548 Details : Each element in 'in0' is added to 'in1' and result is written
1551 #define ADD2(in0, in1, in2, in3, out0, out1) { \
1552 out0 = in0 + in1; \
1555 #define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, \
1557 ADD2(in0, in1, in2, in3, out0, out1); \
1562 Arguments : Inputs - in0, in1, in2, in3
1564 Details : Each element in 'in1' is subtracted from 'in0' and result is
1567 #define SUB2(in0, in1, in2, in3, out0, out1) { \
1568 out0 = in0 - in1; \
1571 #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, \
1573 out0 = in0 - in1; \
1626 Arguments : Inputs - in0, in1, in2, in3
1630 #define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) { \
1632 out1 = in1 + in2; \
1634 out2 = in1 - in2; \
1643 #define BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7, \
1646 out1 = in1 + in6; \
1652 out6 = in1 - in6; \
1661 #define BUTTERFLY_16(in0, in1, in2, in3, in4, in5, in6, in7, \
1666 out1 = in1 + in14; \
1680 out14 = in1 - in14; \
1685 Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
1689 #define TRANSPOSE8x8_UB(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1694 ILVR_B4_SB(in2, in0, in3, in1, in6, in4, in7, in5, \
1706 Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7,
1711 #define TRANSPOSE16x8_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7, \
1717 ILVEV_D2_UB(in0, in8, in1, in9, out7, out6); \
1753 Arguments : Inputs - in0, in1, in2, in3
1757 #define TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, out0, out1, out2, out3) { \
1760 ILVR_H2_SH(in1
1767 Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
1771 #define TRANSPOSE4X8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, \
1777 ILVR_H4_SH(in1, in0, in3, in2, in5, in4, in7, in6, \
1794 Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
1798 #define TRANSPOSE8X4_SH_SH(in0, in1, in2, in3, out0, out1, out2, out3) { \
1801 ILVR_H2_SH(in1, in0, in3, in2, tmp0_m, tmp1_m); \
1802 ILVL_H2_SH(in1, in0, in3, in2, tmp2_m, tmp3_m); \
1808 Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7
1812 #define TRANSPOSE8x8_H(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
1822 ILVR_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \
1824 ILVL_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \
1836 Arguments : Inputs - in0, in1, in2, in3
1840 #define TRANSPOSE4x4_SW_SW(in0, in1, in2, in3, out0, out1, out2, out3) { \
1843 ILVRL_W2_SW(in1, in0, s0_m, s1_m); \
1853 Arguments : Inputs - in0, in1, in2, in3, pdst, stride
1857 #define ADDBLK_ST4x4_UB(in0, in1, in2, in3, pdst, stride) { \
1864 ILVR_D2_SH(in1, in0, in3, in2, inp0_m, inp1_m) \
1876 Arguments : Inputs - in0, in1
1879 Details : Signed byte even elements from 'in0' and 'in1' are packed
1883 #define PCKEV_XORI128_UB(in0, in1) ({ \
1886 out_m = (v16u8)__msa_pckev_b((v16i8)in1, (v16i8)in0); \
1893 Arguments : Inputs - in0, in1, in2, in3, dst0, dst1, dst2, dst3,
1896 #define CONVERT_UB_AVG_ST8x4_UB(in0, in1, in2, in3, \
1901 tmp0_m = PCKEV_XORI128_UB(in0, in1); \
1910 Arguments : Inputs - in0, in1, pdst
1912 #define PCKEV_ST_SB(in0, in1, pdst) { \
1915 tmp_m = __msa_pckev_b((v16i8)in1, (v16i8)in0); \
1920 Arguments : Inputs - in0, in1, mask, coeff, shift
1922 #define HORIZ_2TAP_FILT_UH(in0, in1, mask, coeff, shift) ({ \
1926 tmp0_m = __msa_vshf_b((v16i8)mask, (v16i8)in1, (v16i8)in0); \
