Lines Matching refs:Def
146 /// \brief Track Def -> Use info used for rewriting copies.
278 /// follows the use-def chain to find successive suitable sources.
280 /// def = COPY src.
285 /// def = COPY v2.sub0
287 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
290 /// Then, def can be rewritten into def = COPY v0.
293 /// The current point into the use-def chain.
294 const MachineInstr *Def;
295 /// The index of the definition in Def.
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
357 Def = MRI.getVRegDef(Reg);
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
375 assert(DefIdx < Def->getDesc().getNumDefs() &&
376 Def->getOperand(DefIdx).isReg() && "Invalid definition");
377 Reg = Def->getOperand(DefIdx).getReg();
380 /// \brief Following the use-def chain, get the next available source
503 // Both will be live out of the def MBB anyway. Don't extend live range of
609 /// retrieve all Def -> Use along the way up to the next source. Any found
645 // Follow the chain of copies until we reach the top of the use-def chain
651 // Insert the Def -> Use entry for the recently found source.
695 // one use-def which cannot be rewritten.
712 /// from its edges. By inserting a new PHI, we provide a rewritten PHI def
813 /// \brief Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
815 /// multiple sources for a given \p Def are found along the way, we found a
821 TargetInstrInfo::RegSubRegPair Def,
825 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
854 // Build the new PHI node and return its def register as the new source.
868 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
874 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
896 /// \brief Get the next rewritable def source (TrackReg, TrackSubReg)
923 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
929 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
931 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
936 getNewSource(&MRI, &TII, Def, RewriteMap);
939 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg);
947 NewCopy->getOperand(0).setSubReg(Def.SubReg);
948 if (Def.SubReg)
954 MRI.replaceRegWith(Def.Reg, NewVR);
1272 TargetInstrInfo::RegSubRegPair Def(CopyDefReg, CopyDefSubReg);
1273 if (!findNextSource(Def.Reg, Def.SubReg, RewriteMap))
1276 RewritePairs.push_back(Def);
1280 for (const auto &Def : RewritePairs) {
1282 MachineInstr *NewCopy = CpyRewriter->RewriteSource(Def, RewriteMap);
1338 /// and only if the def and use are in the same BB.
1545 const auto &Def = NAPhysToVirtMIs.find(Reg);
1546 if (Def != NAPhysToVirtMIs.end()) {
1551 NAPhysToVirtMIs.erase(Def);
1557 unsigned Def = RegMI.first;
1558 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1561 NAPhysToVirtMIs.erase(Def);
1674 assert(Def->isCopy() && "Invalid definition");
1675 // Copy instruction are supposed to be: Def = Src.
1677 assert(Def->getNumOperands() == 2 && "Invalid number of operands");
1679 if (Def
1684 const MachineOperand &Src = Def->getOperand(1);
1689 assert(Def->isBitcast() && "Invalid definition");
1692 if (Def->hasUnmodeledSideEffects())
1695 // Bitcasts with more than one def are not supported.
1696 if (Def->getDesc().getNumDefs() != 1)
1698 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1703 unsigned SrcIdx = Def->getNumOperands();
1706 const MachineOperand &MO = Def->getOperand(OpIdx);
1718 const MachineOperand &Src = Def->getOperand(SrcIdx);
1723 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1726 if (Def->getOperand(DefIdx).getSubReg())
1728 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1732 // Def.sub0 =
1733 // Def.sub1 =
1734 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1735 // Def. Thus, it must not be generated.
1737 // Def.sub0 (i.e, not defining the other subregs) and we would
1749 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1753 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1772 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1775 if (Def->getOperand(DefIdx).getSubReg())
1788 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1792 // Def = INSERT_SUBREG v0, v1, sub1
1804 const MachineOperand &MODef = Def->getOperand(DefIdx);
1805 // If the result register (Def) and the base register (v0) do not
1820 // we used for Def.
1825 assert((Def->isExtractSubreg() ||
1826 Def->isExtractSubregLike()) && "Invalid definition");
1828 // Def = EXTRACT_SUBREG v0, sub0
1841 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1853 assert(Def->isSubregToReg() && "Invalid definition");
1855 // Def = SUBREG_TO_REG Imm, v0, sub0
1861 if (DefSubReg != Def->getOperand(3).getImm())
1865 if (Def->getOperand(2).getSubReg())
1868 return ValueTrackerResult(Def->getOperand(2).getReg(),
1869 Def->getOperand(3).getImm());
1874 assert(Def->isPHI() && "Invalid definition");
1879 if (Def->getOperand(0).getSubReg() != DefSubReg)
1883 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
1884 auto &MO = Def->getOperand(i);
1893 assert(Def && "This method needs a valid definition");
1896 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
1897 Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
1898 if (Def->isCopy())
1900 if (Def->isBitcast())
1906 if (Def->isRegSequence() || Def->isRegSequenceLike())
1908 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
1910 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
1912 if (Def->isSubregToReg())
1914 if (Def->isPHI())
1920 // If we reach a point where we cannot move up in the use-def chain,
1922 if (!Def)
1933 // Update the result before moving up in the use-def chain
1935 Res.setInst(Def);
1937 // If we can still move up in the use-def chain, move to the next
1940 Def = MRI.getVRegDef(Reg);
1948 // early by cutting the use-def chain.
1949 Def = nullptr;
