Lines Matching defs:SRL
1116 else if (Opc == ISD::SRL)
1387 case ISD::SRL: return visitSRL(N);
1486 case ISD::SRL:
2281 SDValue SRL =
2282 DAG.getNode(ISD::SRL, DL, VT, SGN,
2285 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL);
2286 AddToWorklist(SRL.getNode());
2347 return DAG.getNode(ISD::SRL, DL, VT, N0,
2362 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
2505 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2541 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2620 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2651 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2748 // For each of OP in SHL/SRL/SRA/AND...
2752 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2939 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3261 // fold (and (sra)) -> (and (srl)) when possible.
3305 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3328 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3331 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3355 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3357 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3370 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3396 // Make sure everything beyond the low halfword gets set to zero since the SRL
3417 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
3435 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3458 if (N0.getOpcode() != ISD::SRL)
3480 } else { // Opc == ISD::SRL
3571 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
3820 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3831 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3952 // (srl x, (*ext (sub 32, y)))) ->
3956 // (srl x, (*ext y))) ->
3981 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3998 // Canonicalize shl to left side in a shl/srl pair.
4011 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
4012 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
4282 BinOpLHSVal->getOpcode() != ISD::SRL) ||
4459 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4463 N0.getOperand(0).getOpcode() == ISD::SRL) {
4485 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
4499 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4500 // (and (srl x, (sub c1, c2), MASK)
4503 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4518 Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4655 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
4673 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4676 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4703 // If the sign bit is known to be zero, switch this to a SRL.
4705 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4729 // fold (srl c1, c2) -> c1 >>u c2
4732 return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C);
4733 // fold (srl 0, x) -> 0
4736 // fold (srl x, c >= size(x)) -> undef
4739 // fold (srl x, 0) -> x
4742 // if (srl x, c) is known to be zero, return 0
4747 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4748 if (N1C && N0.getOpcode() == ISD::SRL) {
4755 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4760 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4762 N0.getOperand(0).getOpcode() == ISD::SRL &&
4776 DAG.getNode(ISD::SRL, DL, InnerShiftVT,
4783 // fold (srl (shl x, c), c) -> (and x, cst2)
4794 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4802 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4805 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT,
4818 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4822 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4825 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4832 // zeros, thus the result of the srl will always be zero.
4843 // could be set on input to the CTLZ node. If this bit is set, the SRL
4844 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4845 // to an SRL/XOR pair, which is likely to simplify more.
4851 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
4863 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4867 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4870 // fold operands of srl based on knowledge that the low bits are not
4879 // Attempt to convert a srl of a load into a narrower zero-extending load.
4887 // %c = srl i32 %b, 1
4897 // However when after the source operand of SRL is optimized into AND, the SRL
5975 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
6257 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
6273 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
6493 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
6540 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
6698 case ISD::SRL:
6710 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
6739 } else if (Opc == ISD::SRL) {
6740 // Another special-case: SRL is basically zero-extending a narrower value.
6759 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6773 // Because a SRL must be assumed to *need* to zero-extend the high bits
6775 // lowering of SRL and an sextload.
6935 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6939 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6940 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6941 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6942 if (N0.getOpcode() == ISD::SRL) {
6945 // We can turn this into an SRA iff the input to the SRL is already sign
7138 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
7400 X = DAG.getNode(ISD::SRL, DL,
9340 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
9343 N1.getOperand(0).getOpcode() == ISD::SRL))) {
9355 // %c = srl i32 %b, 1
9366 // SRL constant is equal to the log2 of the AND constant. The back-end is
9395 // Replace the uses of SRL with SETCC
10061 /// Shift = srl Ty1 Origin, CstTy Amount
10531 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
10701 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal,
14078 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
14085 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
