Lines Matching refs:getOpcode
136 if (N->getOpcode() == ISD::HANDLENODE)
573 if (Op.getOpcode() == ISD::FNEG) return 2;
581 switch (Op.getOpcode()) {
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
644 switch (Op.getOpcode()) {
687 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
693 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
700 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
718 if (N.getOpcode() == ISD::SETCC) {
725 if (N.getOpcode() != ISD::SELECT_CC ||
827 if (N0.getOpcode() == Opc) {
847 if (N1.getOpcode() == Opc) {
977 unsigned Opc = Op.getOpcode();
1044 unsigned Opc = Op.getOpcode();
1102 unsigned Opc = Op.getOpcode();
1146 unsigned Opc = Op.getOpcode();
1160 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1175 unsigned Opc = Op.getOpcode();
1322 assert(N->getOpcode() != ISD::DELETED_NODE &&
1323 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1357 switch (N->getOpcode()) {
1458 assert(N->getOpcode() != ISD::DELETED_NODE &&
1461 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1462 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1474 switch (N->getOpcode()) {
1503 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1511 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1562 switch (Op.getOpcode()) {
1656 if (N0.getOpcode() == ISD::UNDEF)
1658 if (N1.getOpcode() == ISD::UNDEF)
1675 GA->getOpcode() == ISD::GlobalAddress)
1680 if (N1C && N0.getOpcode() == ISD::SUB)
1692 if (N0.getOpcode() == ISD::SUB && isNullConstant(N0.getOperand(0)))
1695 if (N1.getOpcode() == ISD::SUB && isNullConstant(N1.getOperand(0)))
1698 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1701 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1704 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1709 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1714 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1715 N1.getOperand(0).getOpcode() == ISD::SUB &&
1717 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1721 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1742 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
1748 if (N0.getOpcode() == ISD::SHL && N0.getOperand(0).getOpcode() == ISD::SUB &&
1755 if (N1.getOpcode() == ISD::AND) {
1769 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1778 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1845 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1897 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1900 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1903 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1906 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1908 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1916 if (N0.getOpcode() == ISD::ADD &&
1917 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1918 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1920 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1923 if (N0.getOpcode() == ISD::ADD &&
1924 N0.getOperand(1).getOpcode() == ISD::ADD &&
1929 if (N0.getOpcode() == ISD::SUB &&
1930 N0.getOperand(1).getOpcode() == ISD::SUB &&
1936 if (N0.getOpcode() == ISD::UNDEF)
1938 if (N1.getOpcode() == ISD::UNDEF)
1945 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1957 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2004 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2016 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2093 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2108 if (N0.getOpcode() == ISD::SHL &&
2113 } else if (N1.getOpcode() == ISD::SHL &&
2129 N0.getOpcode() == ISD::ADD &&
2170 unsigned Opcode = Node->getOpcode();
2203 unsigned UserOpc = User->getOpcode();
2317 if (N0.getOpcode() == ISD::UNDEF)
2320 if (N1.getOpcode() == ISD::UNDEF)
2352 if (N1.getOpcode() == ISD::SHL) {
2381 if (N0.getOpcode() == ISD::UNDEF)
2384 if (N1.getOpcode() == ISD::UNDEF)
2392 unsigned Opcode = N->getOpcode();
2421 if (N1.getOpcode() == ISD::SHL) {
2451 assert((OptimizedDiv.getOpcode() != ISD::UDIVREM) &&
2452 (OptimizedDiv.getOpcode() != ISD::SDIVREM));
2465 if (N0.getOpcode() == ISD::UNDEF)
2468 if (N1.getOpcode() == ISD::UNDEF)
2492 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2528 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2585 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2595 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2698 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
2703 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
2713 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2728 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2729 N0.getOpcode() == ISD::SIGN_EXTEND ||
2730 N0.getOpcode() == ISD::BSWAP ||
2732 (N0.getOpcode() == ISD::ANY_EXTEND &&
2733 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2734 (N0.getOpcode() == ISD::TRUNCATE &&
2740 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2741 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2745 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2752 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2753 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2755 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2759 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2770 if ((N0.getOpcode() == ISD::BITCAST ||
2771 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2781 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2782 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2800 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2817 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2828 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2838 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2849 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2870 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2939 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3063 if (N1C && N0.getOpcode() == ISD::OR)
3068 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3092 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
3094 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
3095 N0.getOpcode() == ISD::LOAD) {
3096 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
3195 if (N1C && (N0.getOpcode() == ISD::LOAD ||
3196 (N0.getOpcode() == ISD::ANY_EXTEND &&
3197 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
3198 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
3256 if (N0.getOpcode() == N1.getOpcode())
3306 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3331 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3333 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3335 if (N0.getOpcode() == ISD::AND) {
3345 if (N1.getOpcode() == ISD::AND) {
3355 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3357 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3372 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3383 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3434 unsigned Opc = N.getOpcode();
3458 if (N0.getOpcode() != ISD::SRL)
3466 if (N0.getOpcode() != ISD::SHL)
3516 if (N0.getOpcode() != ISD::OR)
3522 if (N1.getOpcode() == ISD::OR &&
3544 if (N00.getOpcode() != ISD::OR)
3580 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3631 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
3658 if (N0.getOpcode() == ISD::AND &&
3659 N1.getOpcode() == ISD::AND &&
3791 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3804 if (N0.getOpcode() == N1.getOpcode())
3822 if (Op.getOpcode() == ISD::AND) {
3831 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3881 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
3891 if (Neg.getOpcode() != ISD::SUB)
3900 if (MaskLoBits && Pos.getOpcode() == ISD::AND)
3927 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
3995 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3999 if (RHSShift.getOpcode() == ISD::SHL) {
4054 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
4055 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
4056 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
4057 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
4058 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
4059 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
4060 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
4061 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
4097 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
4100 if (N0.getOpcode() == ISD::UNDEF)
4102 if (N1.getOpcode() == ISD::UNDEF)
4129 switch (N0.getOpcode()) {
4142 if (isOneConstant(N1) && N0.getOpcode() == ISD::ZERO_EXTEND &&
4155 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4158 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4167 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4170 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4178 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
4186 if (N1C && N0.getOpcode() == ISD::XOR) {
4222 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL
4230 if (N0.getOpcode() == N1.getOpcode())
4254 switch (LHS->getOpcode()) {
4264 if (N->getOpcode() != ISD::SHL)
4280 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
4281 BinOpLHSVal->getOpcode() != ISD::SRA &&
4282 BinOpLHSVal->getOpcode() != ISD::SRL) ||
4292 if (N->getOpcode() == ISD::SRA) {
4302 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
4308 SDValue NewShift = DAG.getNode(N->getOpcode(),
4313 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4317 assert(N->getOpcode() == ISD::TRUNCATE);
4318 assert(N->getOperand(0).getOpcode() == ISD::AND);
4344 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4345 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4348 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4370 if (N0.getOpcode() == ISD::AND) {
4375 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4402 if (N0.getOpcode() == ISD::UNDEF)
4409 if (N1.getOpcode() == ISD::TRUNCATE &&
4410 N1.getOperand(0).getOpcode() == ISD::AND) {
4420 if (N1C && N0.getOpcode() == ISD::SHL) {
4437 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4438 N0.getOpcode() == ISD::ANY_EXTEND ||
4439 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4440 N0.getOperand(0).getOpcode() == ISD::SHL) {
4452 DAG.getNode(N0.getOpcode(), DL, VT,
4462 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4463 N0.getOperand(0).getOpcode() == ISD::SRL) {
4485 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
4494 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0),
4503 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4528 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4543 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4552 if (N1C && N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
4600 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4613 if (N1C && N0.getOpcode() == ISD::SRA) {
4629 if (N0.getOpcode() == ISD::SHL && N1C) {
4666 if (N1.getOpcode() == ISD::TRUNCATE &&
4667 N1.getOperand(0).getOpcode() == ISD::AND) {
4675 if (N0.getOpcode() == ISD::TRUNCATE &&
4676 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4677 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4748 if (N1C && N0.getOpcode() == ISD::SRL) {
4761 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4762 N0.getOperand(0).getOpcode() == ISD::SRL &&
4784 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4795 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4821 if (N0.getOpcode() == ISD::SRA)
4826 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4864 if (N1.getOpcode() == ISD::TRUNCATE &&
4865 N1.getOperand(0).getOpcode() == ISD::AND) {
4902 if (Use->getOpcode() == ISD::BRCOND)
4904 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4907 if (Use->getOpcode() == ISD::BRCOND)
4923 if (N0.getOpcode() == ISD::BSWAP)
5104 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
5114 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
5125 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
5144 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
5165 if (N0.getOpcode() == ISD::SETCC) {
5210 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
5211 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
5225 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
5226 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
5227 Cond.getOpcode() == ISD::BUILD_VECTOR);
5241 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5253 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5285 if (Mask.getOpcode() != ISD::SETCC)
5346 if (Mask.getOpcode() == ISD::SETCC) {
5420 if (Mask.getOpcode() != ISD::SETCC)
5497 if (Mask.getOpcode() == ISD::SETCC) {
5580 if (N0.getOpcode() == ISD::SETCC) {
5588 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
5591 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
5613 if (N0.getOpcode() == ISD::SETCC) {
5626 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
5627 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
5647 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5648 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5680 } else if (SCC->getOpcode() == ISD::UNDEF) {
5684 } else if (SCC.getOpcode() == ISD::SETCC) {
5713 if (Carry.getOpcode() == ISD::CARRY_FALSE)
5728 unsigned Opcode = N->getOpcode();
5760 if (Op->getOpcode() == ISD::UNDEF) {
5797 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5820 if (User->getOpcode() == ISD::CopyToReg)
5829 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5869 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
5870 N->getOpcode() == ISD::ZERO_EXTEND) &&
5890 if (N0->getOpcode() != ISD::LOAD)
5901 if (!ExtendUsesToFormExtLoad(N, N0, N->getOpcode(), SetCCs, TLI))
5905 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
5955 (ISD::NodeType)N->getOpcode());
5969 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5973 if (N0.getOpcode() == ISD::TRUNCATE) {
6080 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
6081 N0.getOpcode() == ISD::XOR) &&
6083 N0.getOperand(1).getOpcode() == ISD::Constant &&
6085 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
6101 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
6115 if (N0.getOpcode() == ISD::SETCC) {
6189 if (N->getOpcode() == ISD::TRUNCATE) {
6195 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
6228 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
6258 if (N0.getOpcode() == ISD::TRUNCATE) {
6271 if (N0.getOpcode() == ISD::TRUNCATE) {
6314 if (N0.getOpcode() == ISD::AND &&
6315 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6316 N0.getOperand(1).getOpcode() == ISD::Constant &&
6372 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
6373 N0.getOpcode() == ISD::XOR) &&
6375 N0.getOperand(1).getOpcode() == ISD::Constant &&
6377 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
6383 if (N0.getOpcode() == ISD::AND) {
6404 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
6439 if (N0.getOpcode() == ISD::SETCC) {
6493 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
6495 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
6499 if (N0.getOpcode() == ISD::SHL) {
6515 return DAG.getNode(N0.getOpcode(), DL, VT,
6534 if (N0.getOpcode() == ISD::ANY_EXTEND ||
6535 N0.getOpcode() == ISD::ZERO_EXTEND ||
6536 N0.getOpcode() == ISD::SIGN_EXTEND)
6537 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
6541 if (N0.getOpcode() == ISD::TRUNCATE) {
6554 if (N0.getOpcode() == ISD::TRUNCATE) {
6565 if (N0.getOpcode() == ISD::AND &&
6566 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6567 N0.getOperand(1).getOpcode() == ISD::Constant &&
6613 if (N0.getOpcode() == ISD::LOAD &&
6632 if (N0.getOpcode() == ISD::SETCC) {
6679 switch (V.getOpcode()) {
6723 unsigned Opc = N->getOpcode();
6759 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6790 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6910 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6918 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6942 if (N0.getOpcode() == ISD::SRL) {
6987 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
7002 if (N0.getOpcode() == ISD::UNDEF)
7024 if (N0.getOpcode() == ISD::TRUNCATE)
7027 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
7028 N0.getOpcode() == ISD::SIGN_EXTEND ||
7029 N0.getOpcode() == ISD::ANY_EXTEND) {
7032 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
7052 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7082 if (N0.getOpcode() == ISD::SELECT) {
7099 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
7100 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
7139 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
7160 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
7168 if (X.getOpcode() != ISD::UNDEF) {
7210 if (Elt.getOpcode() != ISD::MERGE_VALUES)
7218 assert(N->getOpcode() == ISD::BUILD_PAIR);
7263 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
7288 if (N0.getOpcode() == ISD::BITCAST)
7329 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
7330 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
7343 if (N0.getOpcode() == ISD::FNEG) {
7347 assert(N0.getOpcode() == ISD::FABS);
7362 if (N0.getOpcode() == ISD::FNEG)
7365 assert(N0.getOpcode() == ISD::FABS);
7381 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
7449 if (N0.getOpcode() == ISD::BUILD_PAIR)
7458 N0->getOpcode() == ISD::VECTOR_SHUFFLE &&
7466 if (Op.getOpcode() == ISD::BITCAST &&
7526 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
7583 if (Op.getOpcode() == ISD::UNDEF) continue;
7608 if (Op.getOpcode() == ISD::UNDEF) {
7660 if (Aggressive && N0.getOpcode() == ISD::FMUL &&
7661 N1.getOpcode() == ISD::FMUL) {
7667 if (N0.getOpcode() == ISD::FMUL &&
7675 if (N1.getOpcode() == ISD::FMUL &&
7684 if (N0.getOpcode() == ISD::FP_EXTEND) {
7686 if (N00.getOpcode() == ISD::FMUL)
7696 if (N1.getOpcode() == ISD::FP_EXTEND) {
7698 if (N10.getOpcode() == ISD::FMUL)
7710 if (N0.getOpcode() == PreferredFusedOpcode &&
7711 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7721 if (N1->getOpcode() == PreferredFusedOpcode &&
7722 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7742 if (N0.getOpcode() == PreferredFusedOpcode) {
7744 if (N02.getOpcode() == ISD::FP_EXTEND) {
7746 if (N020.getOpcode() == ISD::FMUL)
7768 if (N0.getOpcode() == ISD::FP_EXTEND) {
7770 if (N00.getOpcode() == PreferredFusedOpcode) {
7772 if (N002.getOpcode() == ISD::FMUL)
7781 if (N1.getOpcode() == PreferredFusedOpcode) {
7783 if (N12.getOpcode() == ISD::FP_EXTEND) {
7785 if (N120.getOpcode() == ISD::FMUL)
7797 if (N1.getOpcode() == ISD::FP_EXTEND) {
7799 if (N10.getOpcode() == PreferredFusedOpcode) {
7801 if (N102.getOpcode() == ISD::FMUL)
7842 if (N0.getOpcode() == ISD::FMUL &&
7851 if (N1.getOpcode() == ISD::FMUL &&
7859 if (N0.getOpcode() == ISD::FNEG &&
7860 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7873 if (N0.getOpcode() == ISD::FP_EXTEND) {
7875 if (N00.getOpcode() == ISD::FMUL)
7887 if (N1.getOpcode() == ISD::FP_EXTEND) {
7889 if (N10.getOpcode() == ISD::FMUL)
7905 if (N0.getOpcode() == ISD::FP_EXTEND) {
7907 if (N00.getOpcode() == ISD::FNEG) {
7909 if (N000.getOpcode() == ISD::FMUL) {
7927 if (N0.getOpcode() == ISD::FNEG) {
7929 if (N00.getOpcode() == ISD::FP_EXTEND) {
7931 if (N000.getOpcode() == ISD::FMUL) {
7949 if (N0.getOpcode() == PreferredFusedOpcode &&
7950 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7962 if (N1.getOpcode() == PreferredFusedOpcode &&
7963 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7979 if (N0.getOpcode() == PreferredFusedOpcode) {
7981 if (N02.getOpcode() == ISD::FP_EXTEND) {
7983 if (N020.getOpcode() == ISD::FMUL)
8002 if (N0.getOpcode() == ISD::FP_EXTEND) {
8004 if (N00.getOpcode() == PreferredFusedOpcode) {
8006 if (N002.getOpcode() == ISD::FMUL)
8024 if (N1.getOpcode() == PreferredFusedOpcode &&
8025 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {
8027 if (N120.getOpcode() == ISD::FMUL) {
8049 if (N1.getOpcode() == ISD::FP_EXTEND &&
8050 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) {
8054 if (N102.getOpcode() == ISD::FMUL) {
8084 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation");
8109 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
8130 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) {
8206 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
8214 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
8218 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
8225 if (N0.getOpcode() == ISD::FMUL) {
8237 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
8246 if (N1.getOpcode() == ISD::FMUL) {
8258 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
8267 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
8277 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
8289 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
8352 if (N1.getOpcode() == ISD::FADD) {
8409 if (N0.getOpcode() == ISD::FMUL) {
8436 if (N0.getOpcode() == ISD::FADD &&
8517 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) &&
8526 if (N0.getOpcode() == ISD::FMUL &&
8563 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
8604 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
8679 if (N1.getOpcode() == ISD::FSQRT) {
8683 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
8684 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8691 } else if (N1.getOpcode() == ISD::FP_ROUND &&
8692 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8699 } else if (N1.getOpcode() == ISD::FMUL) {
8704 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8707 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
8805 return (N1.getOpcode() == ISD::FP_EXTEND ||
8806 N1.getOpcode() == ISD::FP_ROUND) &&
8837 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
8838 N0.getOpcode() == ISD::FCOPYSIGN)
8843 if (N1.getOpcode() == ISD::FABS)
8847 if (N1.getOpcode() == ISD::FCOPYSIGN)
8884 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
8898 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
8899 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
8939 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
8959 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
8964 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
8965 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
9031 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
9035 if (N0.getOpcode() == ISD::FP_ROUND) {
9062 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
9095 N->use_begin()->getOpcode() == ISD::FP_ROUND)
9103 if (N0.getOpcode() == ISD::FP16_TO_FP &&
9109 if (N0.getOpcode() == ISD::FP_ROUND
9188 N0.getOpcode() == ISD::BITCAST &&
9212 if (N0.getOpcode() == ISD::FMUL &&
9282 if (N0.getOpcode() == ISD::FABS)
9287 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
9293 N0.getOpcode() == ISD::BITCAST &&
9332 if (N1.getOpcode() == ISD::SETCC &&
9340 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
9341 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
9343 N1.getOperand(0).getOpcode() == ISD::SRL))) {
9345 if (N1.getOpcode() == ISD::TRUNCATE) {
9371 if (Op0.getOpcode() == ISD::AND &&
9372 Op1.getOpcode() == ISD::Constant) {
9375 if (AndOp1.getOpcode() == ISD::Constant) {
9411 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
9415 if (Op0.getOpcode() == Op1.getOpcode()) {
9437 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
9440 Op0.getOpcode() == ISD::XOR) {
9483 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
9514 if (N->getOpcode() == ISD::ADD) {
9522 } else if (N->getOpcode() == ISD::SUB) {
9572 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
9633 if (Use.getUser()->getOpcode() != ISD::ADD &&
9634 Use.getUser()->getOpcode() != ISD::SUB) {
9732 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
9733 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
9801 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
9830 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
9894 assert((Inc.getOpcode() != ISD::TargetConstant ||
9897 if (Inc.getOpcode() == ISD::TargetConstant) {
9947 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
10217 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
10321 if (Use->getOpcode() != ISD::BITCAST)
10531 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
10539 if (User->getOpcode() != ISD::TRUNCATE)
10585 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
10587 assert(SliceInst->getOpcode() == ISD::LOAD &&
10606 if (V->getOpcode() != ISD::AND ||
10619 else if (Chain->getOpcode() != ISD::TokenFactor)
10750 unsigned Opc = Value.getOpcode();
10774 Value.getOperand(1).getOpcode() != ISD::Constant)
10955 if (Ptr->getOpcode() != ISD::ADD)
10971 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
10979 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
10985 if (IndexOffset->getOpcode() != ISD::ADD)
10996 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
11035 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use.
11071 if (OtherOp->getOpcode() == ISD::ADD &&
11231 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
11357 bool IsExtractVecSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
11358 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR);
11371 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
11507 unsigned StoreValOpcode = St->getValue().getOpcode();
11759 if (Value.getOpcode() == ISD::TargetConstantFP)
11848 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
11864 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
11964 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
11984 } while (ST->getOpcode() != ISD::DELETED_NODE);
12010 if (InVal.getOpcode() == ISD::UNDEF)
12031 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
12051 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
12054 } else if (InVec.getOpcode() == ISD::UNDEF) {
12160 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
12177 InVec.getOpcode() == ISD::BUILD_VECTOR &&
12198 if (ConstEltNo && InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
12217 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
12246 if (InVec.getOpcode() == ISD::BITCAST) {
12285 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
12312 if (InVec.getOpcode() == ISD::BITCAST) {
12367 if (In.getOpcode() == ISD::UNDEF) continue;
12369 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
12370 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
12420 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
12421 Cast.getOpcode() == ISD::ZERO_EXTEND ||
12422 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
12424 if (Cast.getOpcode() == ISD::UNDEF)
12463 unsigned Opc = In.getOpcode();
12511 if (In.getOpcode() == ISD::UNDEF)
12554 if (Op.getOpcode() == ISD::UNDEF) continue;
12564 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
12591 unsigned Opcode = N->getOperand(i).getOpcode();
12715 if (ISD::BITCAST == Op.getOpcode() &&
12718 else if (ISD::UNDEF == Op.getOpcode())
12744 if (Op.getOpcode() == ISD::UNDEF)
12773 while (Op.getOpcode() == ISD::BITCAST)
12777 if (Op.getOpcode() == ISD::UNDEF) {
12782 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
12793 while (ExtVec.getOpcode() == ISD::BITCAST)
12797 if (ExtVec.getOpcode() == ISD::UNDEF) {
12821 if (SV0.getOpcode() == ISD::UNDEF || SV0 == ExtVec) {
12825 } else if (SV1.getOpcode() == ISD::UNDEF || SV1 == ExtVec) {
12853 return Op.getOpcode() == ISD::UNDEF;
12859 if (In->getOpcode() == ISD::BITCAST &&
12866 if (Scalar->getOpcode() == ISD::TRUNCATE &&
12892 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
12906 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12918 if (ISD::UNDEF == Op.getOpcode())
12921 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12957 if (Op.getOpcode() == ISD::UNDEF)
12961 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
12999 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
13016 if (V->getOpcode() == ISD::BITCAST)
13019 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
13058 switch (V.getOpcode()) {
13157 if (NumElemsPerConcat * 2 == NumElts && N1.getOpcode() == ISD::UNDEF &&
13213 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
13231 if (N0.getOpcode() == ISD::UNDEF) {
13248 if (N1.getOpcode() == ISD::UNDEF) {
13271 if (V->getOpcode() == ISD::BITCAST) {
13278 if (V->getOpcode() == ISD::BUILD_VECTOR) {
13284 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
13322 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
13324 (N1.getOpcode() == ISD::UNDEF ||
13325 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
13342 if (S.getOpcode() == ISD::BUILD_VECTOR && S.hasOneUse()) {
13344 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR && S.hasOneUse()) {
13373 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
13374 N1.getOpcode() == ISD::UNDEF && Level < AfterLegalizeVectorOps &&
13379 while (BC0.getOpcode() == ISD::BITCAST) {
13396 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
13449 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
13450 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
13460 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
13473 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&
13513 if (CurrentVec.getOpcode() == ISD::UNDEF) {
13580 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
13608 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
13609 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
13633 if (N0->getOpcode() == ISD::FP16_TO_FP)
13643 if (N0->getOpcode() == ISD::AND) {
13669 if (N->getOpcode() != ISD::AND)
13672 if (RHS.getOpcode() == ISD::BITCAST)
13675 if (RHS.getOpcode() != ISD::BUILD_VECTOR)
13693 if (Elt.getOpcode() == ISD::UNDEF) {
13760 N->getOpcode(), SDLoc(LHS), LHS.getValueType(), Ops, N->getFlags()))
13772 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
13773 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
13780 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
13794 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
13805 if (SCC.getOpcode() == ISD::SELECT_CC) {
13831 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
13838 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
13845 if (Cmp.getOpcode() == ISD::SETCC) {
13865 if (LHS.getOpcode() != RHS.getOpcode() ||
13873 if (LHS.getOpcode() == ISD::LOAD) {
13898 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
13906 if (TheSelect->getOpcode() == ISD::SELECT) {
14003 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
14009 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
14119 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
14197 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
14201 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
14437 if (Base.getOpcode() == ISD::ADD) {
14600 switch (Chain.getOpcode()) {
14732 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
