Lines Matching refs:And
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
17 // constants into immediate fields is often done, because it's cheap and it
20 // "Fast" instruction selection is able to fail gracefully and transfer
28 // at -O0, the LLVM optimizers are not running, and this makes the
36 // and identifying simple arithmetic operations that can be directly selected
95 /// appended, and clear the local CSE map.
148 // FastISel might fold the use into another instruction and now there is more
179 // Handle integer promotions, though, because they're common and easy.
263 /// already available in a register and must be materialized with new
287 // cache values defined by Instructions across blocks, and other values
318 // Unhandled operand. Halt "fast" selection and bail.
385 // Unhandled type. Halt "fast" selection and bail.
393 // MVT::i1 is special. Allow AND, OR, or XOR because they
395 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
402 // Check if the first operand is a constant, and handle it as "ri". At -O0,
423 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
427 // Check if the second operand is a constant and handle it appropriately.
438 // Transform "urem x, pow2" -> "and x, pow2-1".
442 ISDOpcode = ISD::AND;
467 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
476 // the given ISD opcode and type. Halt "fast" selection and bail.
486 if (!N) // Unhandled operand. Halt "fast" selection and bail.
508 if (!N) // Unhandled operand. Halt "fast" selection and bail.
527 if (!N) // Unhandled operand. Halt "fast" selection and bail.
536 if (!N) // Unhandled operand. Halt "fast" selection and bail.
547 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
552 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
557 if (!N) // Unhandled operand. Halt "fast" selection and bail.
563 if (!N) // Unhandled operand. Halt "fast" selection and bail.
576 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
609 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
611 // have to worry about calling conventions and target-specific lowering code.
620 // Add the <id> and <numBytes> constants.
633 // <id> and <numBytes>).
640 // Add scratch registers as implicit def and early clobber.
761 // Add the <id> and <numBytes> constants.
823 // Add scratch registers as implicit def and early clobber.
969 // and how many bytes a callee cleanup function will pop. If we port
1085 // make an unrelated function call and use the value, because
1139 // If we assign 'a' a vreg and fast isel later on has to use the selection
1249 // Unhandled type. Halt "fast" selection and bail.
1262 // Unhandled operand. Halt "fast" selection and bail.
1291 // Unhandled type. Halt "fast" selection and bail.
1297 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1415 /// (fall-through) successor, and update the CFG.
1439 // happen in degenerate IR and MachineIR forbids to have a block twice in the
1470 // and then bitcast it back to floating-point.
1572 case Instruction::And:
1573 return selectBinaryOp(I, ISD::AND);
1593 // Halt "fast" selection and bail.
1650 // Unhandled instruction. Halt "fast" selection and bail.
1717 /// If that fails, it materializes the immediate into a register and try
1752 // will be the first use and we should be able to mark it as killed.
1755 // later which also use 'Imm' could be after this instruction and therefore
1988 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
2019 // nodes and Machine PHI nodes, but the incoming operands have not been
2036 // Handle integer promotions, though, because they're common and easy.
