Lines Matching refs:Op0
422 unsigned Op0 = getRegForValue(I->getOperand(0));
423 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
445 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
458 ISDOpcode, Op0, Op0IsKill, CF);
473 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
1296 unsigned Op0 = getRegForValue(I->getOperand(0));
1297 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1310 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1316 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1511 const Value *Op0 = EVI->getOperand(0);
1512 Type *AggTy = Op0->getType();
1516 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1519 else if (isa<Instruction>(Op0))
1520 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1678 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/,
1683 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1698 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1703 unsigned FastISel::fastEmit_rf(MVT, MVT, unsigned, unsigned /*Op0*/,
1709 unsigned FastISel::fastEmit_rri(MVT, MVT, unsigned, unsigned /*Op0*/,
1719 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1738 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1759 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill);
1793 const TargetRegisterClass *RC, unsigned Op0,
1798 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1802 .addReg(Op0, getKillRegState(Op0IsKill));
1805 .addReg(Op0, getKillRegState(Op0IsKill));
1814 const TargetRegisterClass *RC, unsigned Op0,
1820 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1825 .addReg(Op0, getKillRegState(Op0IsKill))
1829 .addReg(Op0, getKillRegState(Op0IsKill))
1838 const TargetRegisterClass *RC, unsigned Op0,
1845 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1851 .addReg(Op0, getKillRegState(Op0IsKill))
1856 .addReg(Op0, getKillRegState(Op0IsKill))
1866 const TargetRegisterClass *RC, unsigned Op0,
1871 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1875 .addReg(Op0, getKillRegState(Op0IsKill))
1879 .addReg(Op0, getKillRegState(Op0IsKill))
1888 const TargetRegisterClass *RC, unsigned Op0,
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1898 .addReg(Op0, getKillRegState(Op0IsKill))
1903 .addReg(Op0, getKillRegState(Op0IsKill))
1932 const TargetRegisterClass *RC, unsigned Op0,
1938 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1943 .addReg(Op0, getKillRegState(Op0IsKill))
1948 .addReg(Op0, getKillRegState(Op0IsKill))
1973 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
1976 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1978 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1979 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1981 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1987 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1988 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
