Lines Matching refs:tii
277 const TargetInstrInfo *TII,
307 const MCInstrDesc Desc = TII->get(Opcode);
308 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
409 const TargetInstrInfo *TII) {
419 if (IsChainDependent(Op.getNode(), Inner, NestLevel, TII))
426 (unsigned)TII->getCallFrameDestroyOpcode()) {
429 (unsigned)TII->getCallFrameSetupOpcode()) {
459 const TargetInstrInfo *TII) {
471 MyNestLevel, MyMaxNest, TII))
484 (unsigned)TII->getCallFrameDestroyOpcode()) {
488 (unsigned)TII->getCallFrameSetupOpcode()) {
553 Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
556 SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
758 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
829 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
842 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
971 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
1011 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1200 const TargetInstrInfo *TII) {
1206 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1318 if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
1325 if (!IsChainDependent(Gen, Node, 0, TII) &&
1335 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1458 MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1641 const TargetInstrInfo *TII;
1662 const TargetInstrInfo *tii,
1667 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(nullptr) {
1782 const TargetInstrInfo *tii,
1786 tii, tri, tli),
1972 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
1987 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2034 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2086 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2101 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2164 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2181 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2701 const MCInstrDesc &MCID = TII->get(Opc);
2721 const TargetInstrInfo *TII,
2724 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2757 const TargetInstrInfo *TII,
2760 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2761 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2768 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2880 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
2928 const MCInstrDesc &MCID = TII->get(Opc);
2965 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
2975 if (!canClobberReachingPhysRegUse(SuccSU, SU, scheduleDAG, TII, TRI) &&
2997 const TargetInstrInfo *TII = STI.getInstrInfo();
3001 new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr);
3011 const TargetInstrInfo *TII = STI.getInstrInfo();
3015 new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr);
3025 const TargetInstrInfo *TII = STI.getInstrInfo();
3030 new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3041 const TargetInstrInfo *TII = STI.getInstrInfo();
3046 new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
