Lines Matching refs:And
69 /// and called function attributes.
83 /// Generate a libcall taking the given operands as arguments and returning a
122 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
296 /// constant and return true.
305 case ISD::AND:
332 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
354 // Search for the smallest integer type with free casts to and from
382 /// use this information to simplify Op, create a new simplified DAG node and
383 /// return true, returning the original and new nodes in Old and New. Otherwise,
384 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
430 case ISD::AND:
439 // If the LHS already has zeros where RHSC does, this and is dead.
451 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
455 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
458 // These bits cannot contribute to the result of the 'and'.
482 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
486 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
516 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
520 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
545 // If all of the demanded bits on one side are known, and all of the set
547 // into an AND, as we know the bits will be cleared.
554 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
589 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
590 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
596 // Only known if known in both the LHS and RHS.
607 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
608 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
614 // Only known if known in both the LHS and RHS.
675 // aren't demanded (as above) and that the shifted upper c1 bits of
718 // If the shift is exact, then it does demand the low bits (and knows that
748 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
757 // If this is an arithmetic shift right and only the low-bit is set, we can
776 // If the shift is exact, then it does demand the low bits (and knows that
790 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
834 // extension to be dropped altogether later and do not simplify.
874 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
934 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
988 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
994 // Simplify the input, using demanded bit information, and compute the known
1048 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1060 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1066 // If this is an FP->Int bitcast and if the sign bit is the only
1096 // Add, Sub, and Mul don't demand any bits in positions beyond that
1137 /// in Mask are known to be either zero or one and return them in the
1213 // Only interested in constant splats, and we don't try to handle undef
1243 // Only interested in constant splats, and we don't try to handle undef
1256 /// and cc. If it is unable to simplify it, return a null SDValue.
1278 // Ensure that the constant occurs on the RHS, and fold constant
1289 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1330 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1332 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1349 } else if (N0->getOpcode() == ISD::AND) {
1392 // If the LHS is '(and load, const)', the RHS is 0,
1393 // the test is for equality or unsigned, and all 1 bits of the const are
1397 N0.getOpcode() == ISD::AND && C1 == 0 &&
1443 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1522 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1552 (N0.getOpcode() == ISD::AND &&
1557 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1568 assert(N0.getOpcode() == ISD::AND &&
1571 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1595 if (Op0.getOpcode() == ISD::AND &&
1600 Op0 = DAG.getNode(ISD::AND, dl, VT,
1604 Op0 = DAG.getNode(ISD::AND, dl, VT,
1711 N0.getOpcode() == ISD::AND) {
1719 // Perform the xform if the AND RHS is a single bit.
1743 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1825 // If the comparison was an awkward floating-point == or != and one of
1958 // instruction and X+Z has other uses. It could be an induction variable
1959 // chain, and the transform would increase register pressure.
2010 // Note that where y is variable and is known to have at most
2013 if (N0.getOpcode() == ISD::AND)
2024 if (N1.getOpcode() == ISD::AND)
2054 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2061 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2091 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2208 // is possible and fine if either GV or C are missing.
2283 // otherwise keep searching and return the first class found
2314 /// assembly value into the specific constraints and their prefixes,
2315 /// and also tie in the associated operand values.
2316 /// If this returns an empty vector, and if the constraint string itself
2327 and building up the
2416 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2470 // Check and hook up tied operands, choose constraint code to use.
2520 /// Examine constraint type and operand type and determine a weight value.
2522 /// and the current alternative constraint selected.
2544 /// Examine constraint type and operand type and determine a weight value.
2546 /// and the current alternative constraint selected.
2596 /// Other -> immediates and magic values
2607 /// 1) If there is an 'other' constraint, and if the operand is valid for
2661 /// ComputeConstraintToUse - Determines the constraint code and constraint
2663 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2679 // Labels and constants are handled elsewhere ('X' is the only thing
2776 // If d > 0 and m < 0, add the numerator
2781 // If d < 0 and m > 0, subtract the numerator.
2794 // Extract the sign bit and add it to the quotient
2908 // LL, LH, RL, and RH must be either all NULL or all set to a value.
3023 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3028 ISD::SRA, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3033 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
