Lines Matching refs:Op0
194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
212 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
214 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
216 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
1486 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,
1490 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1492 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1501 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
2063 const Value *Op0 = I->getOperand(0);
2067 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) ||
2074 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
2077 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
2085 SrcReg = getRegForValue(Op0);
3835 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3851 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
3855 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3861 Op0, Op0IsKill, Op1, Op1IsKill,
3865 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3871 Op0, Op0IsKill, Op1, Op1IsKill,
3901 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3925 .addReg(Op0, getKillRegState(Op0IsKill));
3928 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
3973 .addReg(Op0, getKillRegState(Op0IsKill))
3975 Op0 = TmpReg;
3978 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4008 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4032 .addReg(Op0, getKillRegState(Op0IsKill));
4035 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4073 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4074 if (!Op0)
4094 .addReg(Op0, getKillRegState(Op0IsKill))
4096 Op0 = TmpReg;
4099 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4129 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4153 .addReg(Op0, getKillRegState(Op0IsKill));
4156 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4203 .addReg(Op0, getKillRegState(Op0IsKill))
4205 Op0 = TmpReg;
4208 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4559 const Value *Op0 = I->getOperand(0);
4560 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
4566 Op0 = ZExt->getOperand(0);
4569 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
4575 Op0 = SExt->getOperand(0);
4580 unsigned Op0Reg = getRegForValue(Op0);
4583 bool Op0IsKill = hasTrivialKill(Op0);
