Lines Matching defs:Neg
876 case AArch64ISD::NEG: return "AArch64ISD::NEG";
5998 // and NEG) are passed through unmodified. This allows codegen patterns
6570 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
7352 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7358 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
