Lines Matching refs:SetCC
69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
275 setOperationAction(ISD::SETCC, MVT::f16, Promote);
345 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
378 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
550 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
672 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
1244 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1246 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1281 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1292 if (Opcode == ISD::SETCC) {
1333 if (Opcode == ISD::SETCC) {
2247 case ISD::SETCC:
3840 "Unexpected setcc expansion!");
3851 // the true and false operands here. This will allow the setcc to be
3870 // the true and false operands here. This will allow the setcc to be
4070 if (CCVal.getOpcode() == ISD::SETCC) {
7491 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
8088 /// \brief Helper structure to keep track of SetCC information.
8094 /// \brief Helper structure to be able to read SetCC information. If set to
8109 // If this is a setcc, this is straight forward.
8110 if (Op.getOpcode() == ISD::SETCC) {
8150 // Returns true if Op is setcc or zext of setcc.
8159 // (add x, [zext] (setcc cc ...) )
8911 /// %sc = setcc %smax2, %svn3, gt
8936 // Expect N0 is fed by SETCC.
8937 SDValue SetCC = N0.getOperand(0);
8938 EVT SetCCVT = SetCC.getValueType();
8939 if (SetCC.getOpcode() != ISD::SETCC || !SetCCVT.isVector() ||
8943 SDValue VectorOp = SetCC.getOperand(0);
8968 // %sc = setcc %vector, %svn1, gt
8977 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
8990 // Expect to check only lane 0 from the vector SETCC.
9002 return tryMatchAcrossLaneShuffleForReduction(N, SetCC, Op, DAG);
9497 // vselect (v1i1 setcc) ->
9498 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
9506 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9519 SDValue SetCC =
9523 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
9527 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
9529 setcc in the above pattern
9537 if (N0.getOpcode() != ISD::SETCC)
9540 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
9544 "Scalar-SETCC feeding SELECT has unexpected result type!");
9551 // Don't try to do this optimization when the setcc itself has i1 operands.
9564 // This can happen if the SETCC operand size doesn't divide the ResVT size
9580 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
9584 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
