Lines Matching refs:V1
5278 SDValue V1 = Op.getOperand(1);
5282 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5296 if (V1.getValueType().getSizeInBits() == 128) {
5297 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5300 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5410 SDValue V1 = Op.getOperand(0);
5432 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5496 SDValue V1 = Op.getOperand(0);
5500 V1.getValueType().getSimpleVT())) {
5506 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5507 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5508 V1.getOperand(0));
5509 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5511 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5512 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5513 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5516 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5521 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5522 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5523 V1 = V1.getOperand(0);
5524 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5527 V1 = WidenVector(V1.getOperand(Idx), DAG);
5529 V1 = WidenVector(V1, DAG);
5531 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5535 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5537 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5539 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5545 std::swap(V1, V2);
5546 Imm *= getExtFactor(V1);
5547 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5551 Imm *= getExtFactor(V1);
5552 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5559 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5563 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5567 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5572 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5576 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5580 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5589 int NumInputElements = V1.getValueType().getVectorNumElements();
5591 SDValue DstVec = DstIsLeft ? V1 : V2;
5594 SDValue SrcVec = V1;
5632 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7000 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
7077 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7082 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7083 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7084 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7085 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
