Lines Matching refs:getOpcode
738 switch (Op.getOpcode()) {
1024 switch (MI->getOpcode()) {
1189 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
1203 } else if (LHS.getOpcode() == ISD::AND && isNullConstant(RHS) &&
1266 else if (RHS.getOpcode() == ISD::SUB) {
1291 unsigned Opcode = Val->getOpcode();
1332 unsigned Opcode = Val->getOpcode();
1405 bool NeedsNegOutL = LHS->getOpcode() == ISD::OR;
1406 bool NeedsNegOutR = RHS->getOpcode() == ISD::OR;
1553 switch (Op.getOpcode()) {
1576 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1670 if (Sel.getOpcode() != ISD::SELECT_CC)
1672 if (Sel.getOpcode() != ISD::SELECT_CC)
1735 switch (Op.getOpcode()) {
1858 Op.getOpcode(), dl, Op.getValueType(),
1865 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1876 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1892 Op.getOpcode(), dl, Op.getValueType(),
1902 if (Op.getOpcode() == ISD::FP_TO_SINT)
1924 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1930 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1933 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1949 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1963 if (Op.getOpcode() == ISD::SINT_TO_FP)
2056 if (N->getOpcode() != ISD::BUILD_VECTOR)
2079 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2083 N->getOpcode());
2085 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2104 if (N->getOpcode() == ISD::SIGN_EXTEND)
2112 if (N->getOpcode() == ISD::ZERO_EXTEND)
2120 unsigned Opcode = N->getOpcode();
2131 unsigned Opcode = N->getOpcode();
2203 return DAG.getNode(N0->getOpcode(), DL, VT,
2237 switch (Op.getOpcode()) {
3601 unsigned Opc = LHS.getOpcode();
3637 if (LHS.getOpcode() == ISD::AND &&
3653 if (LHS.getOpcode() == ISD::AND &&
3664 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3674 LHS.getOpcode() != ISD::AND) {
3932 } else if (TVal.getOpcode() == ISD::XOR) {
3940 } else if (TVal.getOpcode() == ISD::SUB) {
4048 unsigned Opc = CCVal.getOpcode();
4070 if (CCVal.getOpcode() == ISD::SETCC) {
4403 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4405 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4462 assert(Op.getOpcode() == ISD::SHL_PARTS);
4834 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4865 if (V.getOpcode() == ISD::UNDEF)
4867 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4988 if (Entry.getOpcode() == ISD::UNDEF)
5436 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5506 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5511 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5521 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5524 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5549 } else if (V2->getOpcode() == ISD::UNDEF &&
5774 unsigned Opcode = N->getOpcode();
5801 if (And.getOpcode() != ISD::AND)
5808 unsigned ShiftOpc = Shift.getOpcode();
5958 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6220 if (V.getOpcode() == ISD::UNDEF)
6251 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6331 if (Op0.getOpcode() != ISD::UNDEF && Op0.getOpcode() != ISD::LOAD &&
6342 if (V.getOpcode() == ISD::UNDEF)
6356 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6390 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6495 while (Op.getOpcode() == ISD::BITCAST)
6542 switch (Op.getOpcode()) {
6559 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6567 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6863 if (I->getOpcode() != Instruction::FMul)
6872 !(User->getOpcode() == Instruction::FSub ||
6873 User->getOpcode() == Instruction::FAdd))
6911 if (Val.getOpcode() != ISD::LOAD)
6936 switch (Instr->getOpcode()) {
7303 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7307 N->getOperand(0).getOpcode() == ISD::SRL &&
7347 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7348 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7349 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7490 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7491 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7510 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7555 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7570 if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
7612 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
7634 unsigned Opc = Op->getOpcode();
7694 if (N.getOpcode() == ISD::SHL)
7696 else if (N.getOpcode() == ISD::SRL)
7720 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7764 if (N0.getOpcode() != ISD::AND)
7768 if (N1.getOpcode() != ISD::AND)
7848 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7853 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7863 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7908 N0->getOpcode() == ISD::TRUNCATE &&
7909 N1->getOpcode() == ISD::TRUNCATE) {
7952 if (N1->getOpcode() != ISD::BITCAST)
7988 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8033 switch (N.getOpcode()) {
8063 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
8068 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
8071 return N.getOpcode() == ISD::BITCAST &&
8072 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
8110 if (Op.getOpcode() == ISD::SETCC) {
8121 if (Op.getOpcode() != AArch64ISD::CSEL)
8154 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
8165 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
8222 if (N->getOpcode() == ISD::ADD)
8230 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8231 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8232 LHS.getOpcode() != RHS.getOpcode())
8235 unsigned ExtType = LHS.getOpcode();
8253 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8357 if (AndN.getOpcode() != ISD::AND)
8441 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8442 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
8507 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8524 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8525 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8547 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
8560 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
8672 if (LD->getOpcode() != ISD::LOAD)
8697 if (User->getOpcode() != ISD::ADD
8815 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE) {
8820 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
8827 if (CurOp.getOpcode() != Op && (CurStep != (NumExpectedSteps - 1)))
8931 if (N0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8932 IfTrue.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8933 IfFalse.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8939 if (SetCC.getOpcode() != ISD::SETCC || !SetCCVT.isVector() ||
8944 unsigned Op = VectorOp->getOpcode();
9027 if (N0->getOpcode() != ISD::ADD)
9064 if (User->getOpcode() != ISD::ADD ||
9186 switch(V.getNode()->getOpcode()) {
9373 unsigned CondOpcode = SubsNode->getOpcode();
9384 if (AndNode->getOpcode() != ISD::AND)
9400 if (AddValue.getOpcode() != ISD::ADD)
9457 unsigned CmpOpc = Cmp.getOpcode();
9480 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9481 LHS.getOpcode() == ISD::SRL)
9506 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
9537 if (N0.getOpcode() != ISD::SETCC)
9602 switch (N->getOpcode()) {
9703 if (Copy->getOpcode() == ISD::CopyToReg) {
9710 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
9715 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
9743 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9753 IsInc = (Op->getOpcode() == ISD::ADD);
9840 switch (N->getOpcode()) {
