Lines Matching refs:Const
34 const AMDGPUSubtarget &STI)
182 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
198 MachineInstr * MI, MachineBasicBlock * BB) const {
202 const R600InstrInfo *TII =
203 static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
587 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
626 const SDValue Args[8] = {
667 const R600InstrInfo *TII =
668 static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
868 SelectionDAG &DAG) const {
903 SDValue Vector) const {
921 SelectionDAG &DAG) const {
937 SelectionDAG &DAG) const {
953 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
987 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
1023 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1033 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1062 unsigned mainop, unsigned ovf) const {
1079 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1092 unsigned DwordOffset) const {
1106 bool R600TargetLowering::isZero(SDValue Op) const {
1116 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1265 SelectionDAG &DAG) const {
1288 unsigned &PtrIncr) const {
1314 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1388 const MachineFunction &MF = DAG.getMachineFunction();
1389 const AMDGPUFrameLowering *TFL =
1390 static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
1468 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1514 // We want Const position encoded with the following formula :
1581 const MachineFunction &MF = DAG.getMachineFunction();
1582 const AMDGPUFrameLowering *TFL =
1583 static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
1626 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1642 const SmallVectorImpl<ISD::InputArg> &Ins,
1644 SmallVectorImpl<SDValue> &InVals) const {
1659 const ISD::InputArg &In = Ins[i];
1715 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1716 EVT VT) const {
1806 SDLoc DL) const {
1835 DAGCombinerInfo &DCI) const {
1938 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1939 unsigned Element = Const->getZExtValue();
1945 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1946 unsigned Element = Const->getZExtValue();
2059 const R600InstrInfo *TII =
2060 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2183 SelectionDAG &DAG) const {
2184 const R600InstrInfo *TII =
2185 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
