Lines Matching refs:PHI
25 /// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
40 /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1>
43 /// Now that the result of the PHI instruction is an SGPR, the register
55 /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
60 /// In order to avoid this problem, this pass searches for PHI instructions
62 /// <vgpr> if the user of the PHI's definition register is a vector instruction.
63 /// If the PHI's definition class is constrained to <vgpr> then the coalescer
274 case AMDGPU::PHI: {
275 DEBUG(dbgs() << "Fixing PHI: " << MI);
280 // If a PHI node defines an SGPR and any of its operands are VGPRs,
283 // Also, if a PHI node defines an SGPR and has all SGPR operands
295 // sgpr2 = PHI sgpr0, sgpr1
331 // If we see a PHI instruction that defines an SGPR, then that PHI
334 case AMDGPU::PHI:
