Lines Matching refs:Src0
834 unsigned Src0 = MI->getOperand(1).getReg();
839 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
843 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
897 AMDGPU::OpName::src0);
898 MachineOperand &Src0 = MI->getOperand(Src0Idx);
899 if (!Src0.isReg())
916 // For VOP2 instructions, any operand type is valid to use for src0. Make
917 // sure we can use the src1 as src0.
923 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0))
952 unsigned Reg = Src0.getReg();
953 unsigned SubReg = Src0.getSubReg();
955 Src0.ChangeToImmediate(Src1.getImm());
982 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
987 // immediate. Also, immediate src0 operand is not handled in
1062 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
1067 // We should only expect these to be on src0 due to canonicalizations.
1068 if (Src0->isReg() && Src0->getReg() == Reg) {
1081 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
1082 // src0 -> src2 K
1083 // src1 -> src0
1101 Src0->setReg(Src1Reg);
1102 Src0->setSubReg(Src1SubReg);
1103 Src0->setIsKill(Src1->isKill());
1129 // We can however allow an inline immediate as src0.
1130 if (!Src0->isImm() &&
1131 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1259 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1260 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1267 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1273 .addImm(0) // Src0 mods
1274 .addOperand(*Src0)
1455 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1558 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1561 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1562 if (!compareMachineOp(Src0, Src1) &&
1563 !compareMachineOp(Src0, Src2)) {
1564 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1861 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1862 MachineOperand &Src0 = MI->getOperand(Src0Idx);
1864 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg()))
1868 // VOP2 src0 instructions support all operand types, so we don't need to check
1882 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1883 MachineOperand &Src0 = MI->getOperand(Src0Idx);
1885 // If src0 can be used as src1, commuting will make the operands legal.
1891 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
1904 unsigned Src0Reg = Src0.getReg();
1905 unsigned Src0SubReg = Src0.getSubReg();
1906 bool Src0Kill = Src0.isKill();
1909 Src0.ChangeToImmediate(Src1.getImm());
1911 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
1912 Src0.setSubReg(Src1.getSubReg());
1930 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
2060 // src0 must have the same register class as dst
2063 unsigned Src0 = MI->getOperand(1).getReg();
2065 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
2070 .addReg(Src0);
2655 MachineOperand &Src0 = Inst->getOperand(1);
2661 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2662 MRI.getRegClass(Src0.getReg()) :
2667 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2678 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2694 // We don't need to legalizeOperands here because for a single operand, src0
2709 MachineOperand &Src0 = Inst->getOperand(1);
2716 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2717 MRI.getRegClass(Src0.getReg()) :
2727 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2741 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2805 // We don't need to legalize operands here. src0 for etiher instruction can be
