Lines Matching refs:addReg
369 .addReg(SrcReg, getKillRegState(KillSrc));
376 .addReg(SrcReg, getKillRegState(KillSrc));
382 .addReg(SrcReg, getKillRegState(KillSrc));
390 .addReg(SrcReg, getKillRegState(KillSrc));
412 .addReg(SrcReg, getKillRegState(KillSrc));
463 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
466 Builder.addReg(SrcReg, RegState::Kill | RegState::Implicit);
469 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
566 .addReg(SrcReg) // src
578 .addReg(SrcReg);
588 .addReg(SrcReg) // src
590 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
591 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
672 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
673 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
724 .addReg(InputPtrReg)
727 .addReg(InputPtrReg)
732 .addReg(STmp1)
733 .addReg(STmp0);
736 .addReg(STmp1)
737 .addReg(TIDIGXReg);
740 .addReg(STmp0)
741 .addReg(TIDIGYReg)
742 .addReg(TIDReg);
745 .addReg(TIDReg)
746 .addReg(TIDIGZReg);
757 .addReg(TIDReg);
763 .addReg(TIDReg);
771 .addReg(TIDReg);
813 .addReg(Dst, RegState::Implicit);
816 .addReg(Dst, RegState::Implicit);
820 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
821 .addReg(Dst, RegState::Implicit);
823 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
824 .addReg(Dst, RegState::Implicit);
839 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
840 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
843 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
844 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
866 .addReg(RegLo)
869 .addReg(RegHi)
1019 DstReg) .addReg(SrcReg);
1719 .addReg(SuperReg.getReg(), 0, SubIdx);
1730 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1733 .addReg(NewSuperReg, 0, SubIdx);
2070 .addReg(Src0);
2122 .addReg(Zero64)
2124 .addReg(SRsrcFormatLo)
2126 .addReg(SRsrcFormatHi)
2140 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2141 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
2145 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2146 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
2150 .addReg(NewVAddrLo)
2152 .addReg(NewVAddrHi)
2176 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2203 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2218 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2220 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2262 // Use addReg instead of addOperand
2264 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2273 .addReg(SBase->getReg(), getKillRegState(IsKill),
2275 .addReg(OffsetSGPR);
2278 .addReg(SBase->getReg(), getKillRegState(IsKill),
2286 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2290 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2293 .addReg(SBase->getReg(), getKillRegState(IsKill),
2295 .addReg(OffsetSGPR);
2331 .addReg(RegLo)
2333 .addReg(RegHi)
2391 .addReg(DWord0)
2393 .addReg(DWord1)
2395 .addReg(DWord2)
2397 .addReg(DWord3)
2410 .addReg(SRsrc)
2637 .addReg(Src.getReg());
2640 .addReg(Src.getReg())
2641 .addReg(TmpReg);
2687 .addReg(DestSub0)
2689 .addReg(DestSub1)
2753 .addReg(DestSub0)
2755 .addReg(DestSub1)
2801 .addReg(MidReg);
2836 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2842 .addReg(MidRegLo);
2845 .addReg(MidRegLo)
2847 .addReg(MidRegHi)
2861 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2864 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2866 .addReg(TmpReg)
2990 .addReg(IndirectBaseReg, RegState::Define)
2992 .addReg(IndirectBaseReg)
2993 .addReg(OffsetReg)
2995 .addReg(ValueReg);
3010 .addReg(IndirectBaseReg)
3011 .addReg(OffsetReg)
