Lines Matching refs:getOpcode
82 switch (MI->getOpcode()) {
207 unsigned Opc = LdSt->getOpcode();
474 const unsigned Opcode = MI.getOpcode();
793 switch (MI->getOpcode()) {
896 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
902 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
981 unsigned Opc = MI->getOpcode();
1000 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
1034 unsigned Opc = MI.getOpcode();
1052 unsigned Opc = UseMI->getOpcode();
1255 switch (MI->getOpcode()) {
1360 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1453 uint16_t Opcode = MI->getOpcode();
1556 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1557 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1584 switch (MI.getOpcode()) {
1653 const MCInstrDesc &Desc = get(MI.getOpcode());
1668 switch (MI.getOpcode()) {
1684 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1806 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1847 unsigned Opc = MI->getOpcode();
1927 unsigned Opc = MI->getOpcode();
1981 if (MI->getOpcode() == AMDGPU::PHI) {
2029 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
2061 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
2080 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
2084 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
2164 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
2341 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2343 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2454 unsigned Opcode = Inst->getOpcode();
2825 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2890 switch (Inst.getOpcode()) {
3046 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
