Home | History | Annotate | Download | only in AMDGPU

Lines Matching refs:TRI

113   const SIRegisterInfo &TRI) {
114 PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg(
120 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
121 DispatchPtrUserSGPR = TRI.getMatchingSuperReg(
127 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
128 QueuePtrUserSGPR = TRI.getMatchingSuperReg(
134 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
135 KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg(
146 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
158 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);