Lines Matching refs:addReg
259 .addReg(Reg, RegState::Kill)
264 .addReg(Reg, RegState::Kill)
273 .addReg(Reg, RegState::Kill)
277 .addReg(Reg, RegState::Kill)
285 .addReg(Reg, RegState::Kill)
467 .addImm((unsigned)ARMCC::AL).addReg(0)
469 .addReg(ARM::R4, RegState::Implicit)
479 .addImm((unsigned)ARMCC::AL).addReg(0)
480 .addReg(ARM::R12, RegState::Kill)
481 .addReg(ARM::R4, RegState::Implicit)
488 .addReg(ARM::SP, RegState::Define)
489 .addReg(ARM::R4, RegState::Kill)
663 .addReg(ARM::SP, RegState::Kill));
667 .addReg(ARM::R4, RegState::Kill));
682 .addReg(ARM::SP)
683 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
687 .addReg(ARM::SP));
764 .addReg(ARM::R4));
770 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
774 .addReg(FramePtr));
941 .addReg(ARM::SP).setMIFlags(MIFlags));
943 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
947 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
948 .addReg(ARM::SP).setMIFlags(MIFlags)
1026 .addReg(ARM::SP));
1028 MIB.addReg(Regs[i], getDefRegState(true));
1041 .addReg(ARM::SP, RegState::Define)
1042 .addReg(ARM::SP);
1046 MIB.addReg(0);
1112 .addReg(ARM::SP)
1129 .addReg(ARM::R4);
1146 .addReg(ARM::R4, RegState::Kill).addImm(16)
1147 .addReg(NextReg)
1148 .addReg(SupReg, RegState::ImplicitKill));
1163 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1164 .addReg(SupReg, RegState::ImplicitKill));
1175 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1185 .addReg(NextReg)
1186 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1262 .addReg(ARM::R4, RegState::Define)
1263 .addReg(ARM::R4, RegState::Kill).addImm(16)
1264 .addReg(SupReg, RegState::ImplicitDefine));
1278 .addReg(ARM::R4).addImm(16)
1279 .addReg(SupReg, RegState::ImplicitDefine));
1289 .addReg(ARM::R4).addImm(16));
1297 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1932 .addReg(ScratchReg0).addReg(ScratchReg1);
1935 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
1936 .addReg(ScratchReg0).addReg(ScratchReg1);
1957 .addReg(ARM::SP));
1960 .addReg(ARM::SP)).addReg(0);
1967 .addReg(ScratchReg1).addImm(AlignedStackSize));
1970 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
1986 .addReg(ScratchReg0).addImm(0));
2004 .addReg(ScratchReg0).addImm(4 * TlsOffset));
2011 .addReg(ScratchReg0)
2012 .addReg(ScratchReg1));
2018 .addReg(ARM::CPSR);
2032 .addImm(AlignedStackSize)).addReg(0);
2043 .addReg(0);
2049 .addReg(ARM::LR);
2052 .addReg(ARM::SP, RegState::Define)
2053 .addReg(ARM::SP))
2054 .addReg(ARM::LR);
2081 .addReg(ScratchReg0);
2083 .addReg(ScratchReg0));
2086 .addReg(ARM::LR, RegState::Define)
2087 .addReg(ARM::SP, RegState::Define)
2088 .addReg(ARM::SP)
2093 .addReg(ARM::SP, RegState::Define)
2094 .addReg(ARM::SP))
2095 .addReg(ARM::LR);
2104 .addReg(ScratchReg0)
2105 .addReg(ScratchReg1);
2108 .addReg(ARM::SP, RegState::Define)
2109 .addReg(ARM::SP))
2110 .addReg(ScratchReg0)
2111 .addReg(ScratchReg1);
2127 .addReg(ScratchReg0)
2128 .addReg(ScratchReg1);
2131 .addReg(ARM::SP, RegState::Define)
2132 .addReg(ARM::SP))
2133 .addReg(ScratchReg0)
2134 .addReg(ScratchReg1);
