Lines Matching refs:Reg0
1857 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1869 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1877 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1880 Ops.push_back(Reg0);
1893 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1906 Ops.push_back(Reg0);
1910 Ops.push_back(Reg0);
1984 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2020 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
2029 Ops.push_back(Reg0);
2033 Ops.push_back(Reg0);
2057 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2072 Ops.push_back(Reg0);
2076 Ops.push_back(Reg0);
2148 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2155 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2179 Ops.push_back(Reg0);
2244 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2258 Ops.push_back(Reg0);
2261 Ops.push_back(Reg0);
2347 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2355 getAL(CurDAG, dl), Reg0, Reg0 };
2365 getAL(CurDAG, dl), Reg0, Reg0 };
2372 getAL(CurDAG, dl), Reg0 };
2391 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2395 getAL(CurDAG, dl), Reg0 };
2410 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2414 getAL(CurDAG, dl), Reg0 };
2582 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2584 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2587 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2588 Reg0 };
2599 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2601 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2604 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2605 Reg0 };
3834 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3857 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3872 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
