Lines Matching defs:Lower
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
837 // then set them all for expand so we can lower them later into their
894 // We want to custom lower some of our intrinsics.
1420 /// LowerCallResult - Lower the result values of a call into the
1759 // For tail calls lower the arguments to the 'real' stack slot.
2460 // and pass the lower and high parts through.
2533 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2575 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2788 default: return SDValue(); // Don't custom lower most intrinsics.
4252 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4288 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4542 // Lower vector shifts on NEON to use VSHL.
4580 "Unknown shift to lower!");
4582 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4589 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4869 // swap higher and lower 32 bit word
4911 // possible. Lower it to a splat followed by an extract.
5105 // upper and lower parts of the mask with a matching value for WhichResult
5532 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
6778 SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
6783 Results.push_back(Lower);
6822 lower this!");
6896 llvm_unreachable("Don't know how to custom lower this!");
10147 // Vector shifts: check for immediate versions and lower them.
11354 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11620 // Lower call
11973 // If the index is unknown at compile time, this is very expensive to lower
12074 /// \brief Lower an interleaved load into a vldN intrinsic.
12076 /// E.g. Lower an interleaved load (Factor = 2):
12158 /// \brief Lower an interleaved store into a vstN intrinsic.
12160 /// E.g. Lower an interleaved store (Factor = 3):
