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Lines Matching refs:BaseReg

1494                           unsigned BaseReg, bool BaseKill, bool BaseUndef,
1502       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1508       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1521   unsigned BaseReg = BaseOp.getReg();
1529   bool Errata602117 = EvenReg == BaseReg &&
1562         .addReg(BaseReg, getKillRegState(BaseKill))
1569         .addReg(BaseReg, getKillRegState(BaseKill))
1592         (TRI->regsOverlap(EvenReg, BaseReg))) {
1593       assert(!TRI->regsOverlap(OddReg, BaseReg));
1596                     BaseReg, false, BaseUndef, false, OffUndef,
1600                     BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
1611       if (EvenReg == BaseReg)
1615                     BaseReg, false, BaseUndef, false, OffUndef,
1619                     BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
1912                           unsigned &OddReg, unsigned &BaseReg,
2011                                           unsigned &BaseReg, int &Offset,
2075   BaseReg = Op0->getOperand(1).getReg();
2170         unsigned BaseReg = 0, PredReg = 0;
2177                                              FirstReg, SecondReg, BaseReg,
2192               .addReg(BaseReg);
2206               .addReg(BaseReg);