Lines Matching refs:addReg
512 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
530 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
645 LiveRegs.addReg(R.first);
690 .addReg(Base, getKillRegState(KillOldBase));
693 .addReg(Base, getKillRegState(KillOldBase))
694 .addImm(Pred).addReg(PredReg);
703 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
704 .addImm(Pred).addReg(PredReg);
708 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
709 .addImm(Pred).addReg(PredReg);
712 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
713 .addImm(Pred).addReg(PredReg).addReg(0);
751 MIB.addReg(Base, getDefRegState(true))
752 .addReg(Base, getKillRegState(BaseKill));
762 MIB.addReg(Base, getKillRegState(BaseKill));
765 MIB.addImm(Pred).addReg(PredReg);
768 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
785 MIB.addReg(Regs[0].first, RegState::Define)
786 .addReg(Regs[1].first, RegState::Define);
788 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
789 .addReg(Regs[1].first, getKillRegState(Regs[1].second));
791 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
894 MIB.addReg(ImpDef, RegState::ImplicitDefine);
1203 .addReg(Base, getDefRegState(true)) // WB base register
1204 .addReg(Base, getKillRegState(BaseKill))
1205 .addImm(Pred).addReg(PredReg);
1327 .addReg(Base, getDefRegState(true)) // WB base register
1328 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1329 .addImm(Pred).addReg(PredReg)
1330 .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
1337 .addReg(Base, RegState::Define)
1338 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1342 .addReg(Base, RegState::Define)
1343 .addReg(Base).addReg(0).addImm(Imm).addImm(Pred).addReg(PredReg);
1348 .addReg(Base, RegState::Define)
1349 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1360 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1361 .addReg(Base).addReg(0).addImm(Imm).addImm(Pred).addReg(PredReg);
1365 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1366 .addReg(Base).addImm(Offset).addImm(Pred).addReg
1413 .addReg(BaseOp.getReg(), RegState::Define);
1416 MIB.addReg(BaseOp.getReg(), RegState::Define)
1419 MIB.addReg(BaseOp.getReg(), RegState::Kill)
1420 .addImm(Offset).addImm(Pred).addReg(PredReg);
1501 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1502 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1503 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1507 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1508 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1509 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1562 .addReg(BaseReg, getKillRegState(BaseKill))
1563 .addImm(Pred).addReg(PredReg)
1564 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1565 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
1569 .addReg(BaseReg, getKillRegState(BaseKill))
1570 .addImm(Pred).addReg(PredReg)
1571 .addReg(EvenReg,
1573 .addReg(OddReg,
1843 .addReg(Use.getReg(), RegState::Kill))
2190 .addReg(FirstReg, RegState::Define)
2191 .addReg(SecondReg, RegState::Define)
2192 .addReg(BaseReg);
2197 MIB.addReg(0);
2198 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2204 .addReg(FirstReg)
2205 .addReg(SecondReg)
2206 .addReg(BaseReg);
2211 MIB.addReg(0);
2212 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
