Lines Matching defs:Inst
192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
333 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
377 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1673 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1676 Inst.addOperand(MCOperand::createImm(0));
1678 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1680 Inst.addOperand(MCOperand::createExpr(Expr));
1683 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1685 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1687 Inst.addOperand(MCOperand::createReg(RegNum));
1690 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1692 Inst.addOperand(MCOperand::createImm(getCoproc()));
1695 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1697 Inst.addOperand(MCOperand::createImm(getCoproc()));
1700 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1702 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1705 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1707 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1710 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1712 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1715 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1717 Inst.addOperand(MCOperand::createReg(getReg()));
1720 void addRegOperands(MCInst &Inst, unsigned N) const {
1722 Inst.addOperand(MCOperand::createReg(getReg()));
1725 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1729 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1730 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1731 Inst.addOperand(MCOperand::createImm(
1735 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1739 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1742 Inst.addOperand(MCOperand::createImm(
1746 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1748 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1752 void addRegListOperands(MCInst &Inst, unsigned N) const {
1757 Inst.addOperand(MCOperand::createReg(*I));
1760 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1761 addRegListOperands(Inst, N);
1764 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1765 addRegListOperands(Inst, N);
1768 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1771 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1774 void addModImmOperands(MCInst &Inst, unsigned N) const {
1779 return addImmOperands(Inst, N);
1781 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
1784 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1788 Inst.addOperand(MCOperand::createImm(Enc));
1791 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1795 Inst.addOperand(MCOperand::createImm(Enc));
1798 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1806 Inst.addOperand(MCOperand::createImm(Mask));
1809 void addImmOperands(MCInst &Inst, unsigned N) const {
1811 addExpr(Inst, getImm());
1814 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1817 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
1820 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1823 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
1826 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1830 Inst.addOperand(MCOperand::createImm(Val));
1833 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1838 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1841 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1846 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1849 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1854 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
1857 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1862 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1865 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1870 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1873 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1878 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1881 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1887 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
1890 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1896 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
1899 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1904 Inst.addOperand(MCOperand::createImm(~CE->getValue()));
1907 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1912 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1915 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1920 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1923 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1925 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
1931 Inst.addOperand(MCOperand::createExpr(SR));
1934 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1939 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1945 Inst.addOperand(MCOperand::createExpr(SR));
1951 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
1954 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1956 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
1959 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1961 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
1964 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1966 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
1969 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1972 Inst.addOperand(MCOperand::createImm(Imm));
1975 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1982 Inst.addOperand(MCOperand::createExpr(getImm()));
1988 Inst.addOperand(MCOperand::createImm(Val));
1991 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1993 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
1994 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
1997 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1998 addAlignedMemoryOperands(Inst, N);
2001 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2002 addAlignedMemoryOperands(Inst, N);
2005 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2006 addAlignedMemoryOperands(Inst, N);
2009 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2010 addAlignedMemoryOperands(Inst, N);
2013 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2014 addAlignedMemoryOperands(Inst, N);
2017 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2018 addAlignedMemoryOperands(Inst, N);
2021 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2022 addAlignedMemoryOperands(Inst, N);
2025 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2026 addAlignedMemoryOperands(Inst, N);
2029 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2030 addAlignedMemoryOperands(Inst, N);
2033 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2034 addAlignedMemoryOperands(Inst, N);
2037 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2038 addAlignedMemoryOperands(Inst, N);
2041 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2056 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2057 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2058 Inst.addOperand(MCOperand::createImm(Val));
2061 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2071 Inst.addOperand(MCOperand::createReg(0));
2072 Inst.addOperand(MCOperand::createImm(Val));
2075 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2081 Inst.addOperand(MCOperand::createExpr(getImm()));
2082 Inst.addOperand(MCOperand::createReg(0));
2083 Inst.addOperand(MCOperand::createImm(0));
2099 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2100 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2101 Inst.addOperand(MCOperand::createImm(Val));
2104 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2109 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2110 Inst.addOperand(MCOperand::createImm(Val));
2122 Inst.addOperand(MCOperand::createReg(0));
2123 Inst.addOperand(MCOperand::createImm(Val));
2126 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2132 Inst.addOperand(MCOperand::createExpr(getImm()));
2133 Inst.addOperand(MCOperand::createImm(0));
2144 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2145 Inst.addOperand(MCOperand::createImm(Val));
2148 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2154 Inst.addOperand(MCOperand::createExpr(getImm()));
2155 Inst.addOperand(MCOperand::createImm(0));
2160 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2161 Inst.addOperand(MCOperand::createImm(Val));
2164 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2168 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2169 Inst.addOperand(MCOperand::createImm(Val));
2172 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2175 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2176 Inst.addOperand(MCOperand::createImm(Val));
2179 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2180 addMemImm8OffsetOperands(Inst, N);
2183 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2184 addMemImm8OffsetOperands(Inst, N);
2187 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2191 addExpr(Inst, getImm());
2192 Inst.addOperand(MCOperand::createImm(0));
2198 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2199 Inst.addOperand(MCOperand::createImm(Val));
2202 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2206 addExpr(Inst, getImm());
2207 Inst.addOperand(MCOperand::createImm(0));
2213 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2214 Inst.addOperand(MCOperand::createImm(Val));
2217 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2219 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2220 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2223 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2225 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2226 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2229 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2234 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2235 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2236 Inst.addOperand(MCOperand::createImm(Val));
2239 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2241 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2242 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2243 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2246 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2248 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2249 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2252 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2255 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2256 Inst.addOperand(MCOperand::createImm(Val));
2259 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2262 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2263 Inst.addOperand(MCOperand::createImm(Val));
2266 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2269 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2270 Inst.addOperand(MCOperand::createImm(Val));
2273 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2276 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2277 Inst.addOperand(MCOperand::createImm(Val));
2280 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2288 Inst.addOperand(MCOperand::createImm(Imm));
2291 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2300 Inst.addOperand(MCOperand::createImm(Imm));
2303 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2305 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2306 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2309 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2311 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2317 Inst.addOperand(MCOperand::createImm(Imm));
2320 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2322 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2325 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2327 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2330 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2332 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2335 void addVecListOperands(MCInst &Inst, unsigned N) const {
2337 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2340 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2342 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2343 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2346 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2348 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2351 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2353 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2356 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2358 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2361 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2366 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2369 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2375 Inst.addOperand(MCOperand::createImm(Value));
2378 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2384 Inst.addOperand(MCOperand::createImm(Value));
2387 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2393 Inst.addOperand(MCOperand::createImm(Value));
2396 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2402 Inst.addOperand(MCOperand::createImm(Value));
2405 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2410 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2411 Inst.getOpcode() == ARM::VMOVv16i8) &&
2416 Inst.addOperand(MCOperand::createImm(B));
2418 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2429 Inst.addOperand(MCOperand::createImm(Value));
2432 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2437 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2438 Inst.getOpcode() == ARM::VMOVv16i8) &&
2443 Inst.addOperand(MCOperand::createImm(B));
2445 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2456 Inst.addOperand(MCOperand::createImm(Value));
2459 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2468 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3835 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4618 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4620 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4621 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4629 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4630 Inst.addOperand(Inst.getOperand(0));
4631 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4634 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4637 switch(Inst.getOpcode()) {
4651 switch(Inst.getOpcode()) {
4652 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4653 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4659 switch(Inst.getOpcode()) {
4662 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4666 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4672 switch(Inst.getOpcode()) {
4677 Inst.setOpcode(ARM::t2B);
4684 Inst.setOpcode(ARM::t2Bcc);
4688 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4689 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5643 static bool RequiresVFPRegListValidation(StringRef Inst,
5646 if (Inst.size() < 7)
5649 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5650 StringRef AddressingMode = Inst.substr(4, 2);
5653 AcceptSinglePrecisionOnly = Inst[6] == 's';
5654 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5962 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
5966 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5967 unsigned OpReg = Inst.getOperand(i).getReg();
5977 // Check if the specified regisgter is in the register list of the inst,
5979 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
5980 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
5981 unsigned OpReg = Inst.getOperand(i).getReg();
5990 static bool instIsBreakpoint(const MCInst &Inst) {
5991 return Inst.getOpcode() == ARM::tBKPT ||
5992 Inst.getOpcode() == ARM::BKPT ||
5993 Inst.getOpcode() == ARM::tHLT ||
5994 Inst.getOpcode() == ARM::HLT;
5998 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6004 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6005 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6006 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6021 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6027 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6028 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6043 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6045 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6051 if (inITBlock() && !instIsBreakpoint(Inst)) {
6060 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6076 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6077 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6078 Inst.getOpcode() != ARM::t2Bcc)
6081 const unsigned Opcode = Inst.getOpcode();
6086 const unsigned RtReg = Inst.getOperand(0).getReg();
6100 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6106 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6121 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6122 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6129 const unsigned RmReg = Inst.getOperand(0).getReg();
6138 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6139 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6148 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6149 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6166 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6167 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6189 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6190 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6200 unsigned LSB = Inst.getOperand(2).getImm();
6201 unsigned Widthm1 = Inst.getOperand(3).getImm();
6215 unsigned Rn = Inst.getOperand(0).getReg();
6220 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6234 if (validatetLDMRegList(Inst
6246 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6252 if (validatetLDMRegList(Inst, Operands, 3))
6257 if (validatetSTMRegList(Inst, Operands, 3))
6264 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6269 if (validatetLDMRegList(Inst, Operands, 3))
6272 if (validatetSTMRegList(Inst, Operands, 3))
6281 if (!listContainsReg(Inst, 3, ARM::PC))
6298 // this first statement is always true for the new Inst. Essentially, the
6315 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6319 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6325 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6329 if (validatetSTMRegList(Inst, Operands, 2))
6335 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6348 if (validatetSTMRegList(Inst, Operands, 4))
6356 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6669 bool ARMAsmParser::processInstruction(MCInst &Inst,
6672 switch (Inst.getOpcode()) {
6677 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6681 TmpInst.addOperand(Inst.getOperand(0));
6682 TmpInst.addOperand(Inst.getOperand(1));
6683 TmpInst.addOperand(Inst.getOperand(1));
6686 TmpInst.addOperand(Inst.getOperand(2));
6687 TmpInst.addOperand(Inst.getOperand(3));
6688 Inst = TmpInst;
6695 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6699 TmpInst.addOperand(Inst.getOperand(1));
6700 TmpInst.addOperand(Inst.getOperand(0));
6701 TmpInst.addOperand(Inst.getOperand(1));
6704 TmpInst.addOperand(Inst.getOperand(2));
6705 TmpInst.addOperand(Inst.getOperand(3));
6706 Inst = TmpInst;
6711 if (Inst.getOperand(1).getReg() != ARM::PC ||
6712 Inst.getOperand(5).getReg() != 0 ||
6713 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6717 TmpInst.addOperand(Inst.getOperand(0));
6718 if (Inst.getOperand(2).isImm()) {
6721 unsigned Enc = Inst.getOperand(2).getImm();
6730 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6741 TmpInst.addOperand(Inst.getOperand(3));
6742 TmpInst.addOperand(Inst.getOperand(4));
6743 Inst = TmpInst;
6749 if (Inst.getOperand(1).getImm() > 0 &&
6750 Inst.getOperand(1).getImm() <= 0xff &&
6753 Inst.setOpcode(ARM::tLDRpci);
6755 Inst.setOpcode(ARM::t2LDRpci);
6758 Inst.setOpcode(ARM::t2LDRBpci);
6761 Inst.setOpcode(ARM::t2LDRHpci);
6764 Inst.setOpcode(ARM::t2LDRSBpci);
6767 Inst.setOpcode(ARM::t2LDRSHpci);
6777 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6778 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6779 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6780 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6781 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6782 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6783 TmpInst.addOperand(Inst.getOperand(1)); // lane
6784 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6785 TmpInst.addOperand(Inst.getOperand(6));
6786 Inst = TmpInst;
6799 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6800 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6801 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6802 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6803 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6804 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6805 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6807 TmpInst.addOperand(Inst.getOperand(1)); // lane
6808 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6809 TmpInst.addOperand(Inst.getOperand(6));
6810 Inst = TmpInst;
6823 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6824 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6825 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6826 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6827 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6828 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6829 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6831 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6833 TmpInst.addOperand(Inst.getOperand(1)); // lane
6834 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6835 TmpInst.addOperand(Inst.getOperand(6));
6836 Inst = TmpInst;
6849 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6850 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6851 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6852 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6853 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6854 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6855 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6859 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6861 TmpInst.addOperand(Inst.getOperand(1)); // lane
6862 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6863 TmpInst.addOperand(Inst.getOperand(6));
6864 Inst = TmpInst;
6875 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6876 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6877 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6878 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6880 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6881 TmpInst.addOperand(Inst.getOperand(1)); // lane
6882 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6883 TmpInst.addOperand(Inst.getOperand(5));
6884 Inst = TmpInst;
6897 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6898 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6899 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6900 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6902 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6903 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6905 TmpInst.addOperand(Inst.getOperand(1)); // lane
6906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6907 TmpInst.addOperand(Inst.getOperand(5));
6908 Inst = TmpInst;
6921 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6922 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6923 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6924 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6926 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6927 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6929 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6931 TmpInst.addOperand(Inst.getOperand(1)); // lane
6932 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6933 TmpInst.addOperand(Inst.getOperand(5));
6934 Inst = TmpInst;
6947 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6948 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6949 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6950 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6952 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6953 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6955 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6957 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6959 TmpInst.addOperand(Inst.getOperand(1)); // lane
6960 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6961 TmpInst.addOperand(Inst.getOperand(5));
6962 Inst = TmpInst;
6973 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6974 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6975 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6976 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6977 TmpInst.addOperand(Inst.getOperand(1)); // lane
6978 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6979 TmpInst.addOperand(Inst.getOperand(5));
6980 Inst = TmpInst;
6993 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6994 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6995 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6996 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6997 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6999 TmpInst.addOperand(Inst.getOperand(1)); // lane
7000 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7001 TmpInst.addOperand(Inst.getOperand(5));
7002 Inst = TmpInst;
7015 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7016 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7017 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7018 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7019 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7021 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7023 TmpInst.addOperand(Inst.getOperand(1)); // lane
7024 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7025 TmpInst.addOperand(Inst.getOperand(5));
7026 Inst = TmpInst;
7039 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7040 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7041 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7042 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7043 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7045 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7047 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7049 TmpInst.addOperand(Inst.getOperand(1)); // lane
7050 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7051 TmpInst.addOperand(Inst.getOperand(5));
7052 Inst = TmpInst;
7064 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7065 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7066 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7067 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7068 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7069 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7070 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7071 TmpInst.addOperand(Inst.getOperand(1)); // lane
7072 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7073 TmpInst.addOperand(Inst.getOperand(6));
7074 Inst = TmpInst;
7087 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7088 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7089 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7091 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7092 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7093 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7094 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7095 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7096 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7098 TmpInst.addOperand(Inst.getOperand(1)); // lane
7099 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7100 TmpInst.addOperand(Inst.getOperand(6));
7101 Inst = TmpInst;
7114 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7115 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7116 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7118 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7120 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7121 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7122 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7123 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7124 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7125 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7127 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7129 TmpInst.addOperand(Inst.getOperand(1)); // lane
7130 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7131 TmpInst.addOperand(Inst.getOperand(6));
7132 Inst = TmpInst;
7145 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7146 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7147 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7149 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7151 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7153 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7154 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7155 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7156 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7157 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7158 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7160 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7162 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7164 TmpInst.addOperand(Inst.getOperand(1)); // lane
7165 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7166 TmpInst.addOperand(Inst.getOperand(6));
7167 Inst = TmpInst;
7178 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7179 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7180 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7181 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7182 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7184 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7185 TmpInst.addOperand(Inst.getOperand(1)); // lane
7186 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7187 TmpInst.addOperand(Inst.getOperand(5));
7188 Inst = TmpInst;
7201 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7202 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7203 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7205 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7206 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7207 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7209 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7210 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7212 TmpInst.addOperand(Inst.getOperand(1)); // lane
7213 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7214 TmpInst.addOperand(Inst.getOperand(5));
7215 Inst = TmpInst;
7228 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7229 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7230 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7232 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7234 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7235 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7236 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7238 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7239 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7241 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7243 TmpInst.addOperand(Inst.getOperand(1)); // lane
7244 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7245 TmpInst.addOperand(Inst.getOperand(5));
7246 Inst = TmpInst;
7259 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7260 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7261 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7263 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7265 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7267 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7268 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7269 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7271 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7272 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7274 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7276 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7278 TmpInst.addOperand(Inst.getOperand(1)); // lane
7279 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7280 TmpInst.addOperand(Inst.getOperand(5));
7281 Inst = TmpInst;
7292 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7293 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7294 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7295 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7296 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7297 TmpInst.addOperand(Inst.getOperand(1)); // lane
7298 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7299 TmpInst.addOperand(Inst.getOperand(5));
7300 Inst = TmpInst;
7313 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7314 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7315 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7317 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7318 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7319 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7320 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7322 TmpInst.addOperand(Inst.getOperand(1)); // lane
7323 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7324 TmpInst.addOperand(Inst.getOperand(5));
7325 Inst = TmpInst;
7338 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7339 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7340 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7342 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7344 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7345 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7346 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7347 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7349 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7351 TmpInst.addOperand(Inst.getOperand(1)); // lane
7352 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7353 TmpInst.addOperand(Inst.getOperand(5));
7354 Inst = TmpInst;
7367 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7368 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7369 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7371 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7373 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7375 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7376 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7377 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7378 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7380 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7382 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7384 TmpInst.addOperand(Inst.getOperand(1)); // lane
7385 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7386 TmpInst.addOperand(Inst.getOperand(5));
7387 Inst = TmpInst;
7400 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7401 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7402 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7404 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7406 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7407 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7408 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7409 TmpInst.addOperand(Inst.getOperand(4));
7410 Inst = TmpInst;
7422 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7423 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7424 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7426 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7428 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7429 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7430 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7432 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7433 TmpInst.addOperand(Inst.getOperand(4));
7434 Inst = TmpInst;
7446 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7447 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7448 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7450 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7452 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7453 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7454 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7455 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7456 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7457 TmpInst.addOperand(Inst.getOperand(5));
7458 Inst = TmpInst;
7471 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7472 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7473 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7475 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7477 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7478 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7479 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7480 TmpInst.addOperand(Inst.getOperand(4));
7481 Inst = TmpInst;
7493 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7494 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7495 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7497 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7499 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7500 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7501 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7503 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7504 TmpInst.addOperand(Inst.getOperand(4));
7505 Inst = TmpInst;
7517 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7518 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7519 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7521 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7523 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7524 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7525 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7526 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7527 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7528 TmpInst.addOperand(Inst.getOperand(5));
7529 Inst = TmpInst;
7542 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7543 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7544 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7546 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7548 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7550 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7551 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7552 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7553 TmpInst.addOperand(Inst.getOperand(4));
7554 Inst = TmpInst;
7566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7567 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7568 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7570 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7572 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7574 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7575 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7576 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7578 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7579 TmpInst.addOperand(Inst.getOperand(4));
7580 Inst = TmpInst;
7592 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7593 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7594 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7596 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7598 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7600 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7601 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7602 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7603 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7604 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7605 TmpInst.addOperand(Inst.getOperand(5));
7606 Inst = TmpInst;
7619 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7620 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7621 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7623 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7625 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7627 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7628 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7629 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7630 TmpInst.addOperand(Inst.getOperand(4));
7631 Inst = TmpInst;
7643 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7644 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7645 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7647 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7649 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7651 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7652 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7653 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7655 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7656 TmpInst.addOperand(Inst.getOperand(4));
7657 Inst = TmpInst;
7669 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7670 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7671 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7673 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7675 TmpInst.addOperand(MCOperand::createReg(Inst
7677 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7678 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7679 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7680 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7681 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7682 TmpInst.addOperand(Inst.getOperand(5));
7683 Inst = TmpInst;
7696 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7697 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7698 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7699 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7700 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7702 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7704 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7705 TmpInst.addOperand(Inst.getOperand(4));
7706 Inst = TmpInst;
7718 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7719 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7720 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7721 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7723 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7724 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7726 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7728 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7729 TmpInst.addOperand(Inst.getOperand(4));
7730 Inst = TmpInst;
7742 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7743 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7744 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7745 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7746 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7747 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7748 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7750 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7752 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7753 TmpInst.addOperand(Inst.getOperand(5));
7754 Inst = TmpInst;
7767 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7768 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7769 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7770 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7771 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7773 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7775 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7777 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7778 TmpInst.addOperand(Inst.getOperand(4));
7779 Inst = TmpInst;
7791 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7792 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7793 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7794 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7796 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7797 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7799 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7801 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7803 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7804 TmpInst.addOperand(Inst.getOperand(4));
7805 Inst = TmpInst;
7817 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7818 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7819 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7820 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7821 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7822 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7823 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7825 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7827 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7829 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7830 TmpInst.addOperand(Inst.getOperand(5));
7831 Inst = TmpInst;
7839 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7840 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7841 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7845 switch (Inst.getOpcode()) {
7854 TmpInst.addOperand(Inst.getOperand(0));
7855 TmpInst.addOperand(Inst.getOperand(5));
7856 TmpInst.addOperand(Inst.getOperand(1));
7857 TmpInst.addOperand(Inst.getOperand(2));
7858 TmpInst.addOperand(Inst.getOperand(3));
7859 TmpInst.addOperand(Inst.getOperand(4));
7860 Inst = TmpInst;
7873 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7874 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7875 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7876 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7877 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7881 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7889 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7892 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7893 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7894 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7895 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7896 TmpInst.addOperand(Inst.getOperand(5));
7899 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7900 Inst = TmpInst;
7909 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7910 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7911 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7915 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7923 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7926 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7929 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7930 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7933 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7934 TmpInst.addOperand(Inst.getOperand(4));
7937 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7938 Inst = TmpInst;
7947 switch(Inst.getOpcode()) {
7957 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7958 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7959 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7961 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7962 TmpInst.addOperand(Inst.getOperand(4));
7963 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7964 Inst = TmpInst;
7972 switch(Inst.getOpcode()) {
7980 unsigned Amt = Inst.getOperand(2).getImm();
7988 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7989 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7992 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7993 TmpInst.addOperand(Inst.getOperand(4));
7994 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7995 Inst = TmpInst;
8002 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8003 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8005 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8006 TmpInst.addOperand(Inst.getOperand(3));
8007 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8008 Inst = TmpInst;
8014 if (Inst.getNumOperands() != 5)
8018 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8019 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8020 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8022 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8023 TmpInst.addOperand(Inst.getOperand(3));
8024 Inst = TmpInst;
8030 if (Inst.getNumOperands() != 5)
8034 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8035 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8036 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8038 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8039 TmpInst.addOperand(Inst.getOperand(3));
8040 Inst = TmpInst;
8047 Inst.getNumOperands() == 5) {
8050 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8051 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8052 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8055 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8056 TmpInst.addOperand(Inst.getOperand(3));
8057 Inst = TmpInst;
8065 Inst.getNumOperands() == 5) {
8068 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8069 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8070 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8072 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8073 TmpInst.addOperand(Inst.getOperand(3));
8074 Inst = TmpInst;
8081 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8083 Inst.setOpcode(ARM::t2ADDri);
8084 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8090 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8092 Inst.setOpcode(ARM::t2SUBri);
8093 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8100 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8101 Inst.setOpcode(ARM::tADDi3);
8110 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8111 Inst.setOpcode(ARM::tSUBi3);
8121 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8122 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8123 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8124 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8125 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8130 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8132 TmpInst.addOperand(Inst.getOperand(0));
8133 TmpInst.addOperand(Inst.getOperand(5));
8134 TmpInst.addOperand(Inst.getOperand(0));
8135 TmpInst.addOperand(Inst.getOperand(2));
8136 TmpInst.addOperand(Inst.getOperand(3));
8137 TmpInst.addOperand(Inst.getOperand(4));
8138 Inst = TmpInst;
8148 auto DestReg = Inst.getOperand(0).getReg();
8149 bool Transform = DestReg == Inst.getOperand(1).getReg();
8150 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8155 Inst.getOperand(5).getReg() != 0 ||
8161 TmpInst.addOperand(Inst.getOperand(0));
8162 TmpInst.addOperand(Inst.getOperand(0));
8163 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8164 TmpInst.addOperand(Inst.getOperand(3));
8165 TmpInst.addOperand(Inst.getOperand(4));
8166 Inst = TmpInst;
8172 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8173 Inst.setOpcode(ARM::t2ADDrr);
8174 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8181 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8182 Inst.setOpcode(ARM::tBcc);
8188 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8189 Inst.setOpcode(ARM::t2Bcc);
8195 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8196 Inst.setOpcode(ARM::t2B);
8202 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8203 Inst.setOpcode(ARM::tB);
8212 unsigned Rn = Inst.getOperand(0).getReg();
8217 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8222 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8226 Inst.insert(Inst.begin(),
8227 MCOperand::createReg(Inst.getOperand(0).getReg()));
8236 unsigned Rn = Inst.getOperand(0).getReg();
8238 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8241 Inst.setOpcode(ARM::t2STMIA_UPD);
8251 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8254 Inst.setOpcode(ARM::t2LDMIA_UPD);
8256 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8257 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8262 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8265 Inst.setOpcode(ARM::t2STMDB_UPD);
8267 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8268 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8274 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8275 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8276 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8277 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8278 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8284 TmpInst.addOperand(Inst.getOperand(0));
8285 TmpInst.addOperand(Inst.getOperand(4));
8286 TmpInst.addOperand(Inst.getOperand(1));
8287 TmpInst.addOperand(Inst.getOperand(2));
8288 TmpInst.addOperand(Inst.getOperand(3));
8289 Inst = TmpInst;
8297 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8298 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8299 Inst.getOperand(2).getImm() == ARMCC::AL &&
8300 Inst.getOperand(4).getReg() == ARM::CPSR &&
8305 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8306 TmpInst.addOperand(Inst.getOperand(0));
8307 TmpInst.addOperand(Inst.getOperand(1));
8308 TmpInst.addOperand(Inst.getOperand(2));
8309 TmpInst.addOperand(Inst.getOperand(3));
8310 Inst = TmpInst;
8321 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8322 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8323 Inst.getOperand(2).getImm() == 0 &&
8327 switch (Inst.getOpcode()) {
8337 TmpInst.addOperand(Inst.getOperand(0));
8338 TmpInst.addOperand(Inst.getOperand(1));
8339 TmpInst.addOperand(Inst.getOperand(3));
8340 TmpInst.addOperand(Inst.getOperand(4));
8341 Inst = TmpInst;
8347 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8351 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8355 TmpInst.addOperand(Inst.getOperand(0));
8356 TmpInst.addOperand(Inst.getOperand(1));
8357 TmpInst.addOperand(Inst.getOperand(3));
8358 TmpInst.addOperand(Inst.getOperand(4));
8359 TmpInst.addOperand(Inst.getOperand(5));
8360 Inst = TmpInst;
8372 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8374 switch (Inst.getOpcode()) {
8385 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8389 TmpInst.addOperand(Inst.getOperand(0));
8390 TmpInst.addOperand(Inst.getOperand(1));
8391 TmpInst.addOperand(Inst.getOperand(2));
8392 TmpInst.addOperand(Inst.getOperand(4));
8393 TmpInst.addOperand(Inst.getOperand(5));
8394 TmpInst.addOperand(Inst.getOperand(6));
8395 Inst = TmpInst;
8406 MCOperand &MO = Inst.getOperand(1);
8410 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8419 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8433 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8434 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8435 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8436 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8437 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8442 switch (Inst.getOpcode()) {
8453 TmpInst.addOperand(Inst.getOperand(0));
8454 TmpInst.addOperand(Inst.getOperand(5));
8455 TmpInst.addOperand(Inst.getOperand(1));
8456 TmpInst.addOperand(Inst.getOperand(2));
8457 TmpInst.addOperand(Inst.getOperand(3));
8458 TmpInst.addOperand(Inst.getOperand(4));
8459 Inst = TmpInst;
8472 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8473 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8474 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8475 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8476 Inst.getOperand(5).getReg() == ARM::CPSR) ||
8477 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8482 switch (Inst.getOpcode()) {
8491 TmpInst.addOperand(Inst.getOperand(0));
8492 TmpInst.addOperand(Inst.getOperand(5));
8493 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8494 TmpInst.addOperand(Inst.getOperand(1));
8495 TmpInst.addOperand(Inst.getOperand(2));
8497 TmpInst.addOperand(Inst.getOperand(2));
8498 TmpInst.addOperand(Inst.getOperand(1));
8500 TmpInst.addOperand(Inst.getOperand(3));
8501 TmpInst.addOperand(Inst.getOperand(4));
8502 Inst = TmpInst;
8511 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8514 unsigned Opc = Inst.getOpcode();
8519 assert(MCID.NumOperands == Inst.getNumOperands() &&
8528 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8532 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8535 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8542 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8543 isARMLowRegister(Inst.getOperand(2).getReg()))
8547 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8548 isARMLowRegister(Inst.getOperand(1).getReg()))
8555 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
8557 else if (Inst.getOperand(I).getReg() == ARM::PC)
8575 MCInst Inst;
8578 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8584 if (validateInstruction(Inst, Operands)) {
8598 while (processInstruction(Inst, Operands, Out))
8603 !isV8EligibleForIT(&Inst)) {
8615 if (Inst.getOpcode() == ARM::ITasm)
8618 Inst.setLoc(IDLoc);
8619 Out.EmitInstruction(Inst, getSTI());
8780 else if (IDVal == ".inst")
8782 else if (IDVal == ".inst.n")
8784 else if (IDVal == ".inst.w")
9483 /// ::= .inst opcode [, ...]
9484 /// ::= .inst.n opcode [, ...]
9485 /// ::= .inst.w opcode [, ...]
9501 "use inst.n/inst.w instead");
9536 Error(Loc, "inst.n operand is too big, use inst.w instead");
9543 inst.w" : "inst") + " operand is too big");
