Lines Matching defs:Rm
1130 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1135 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1167 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1467 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1529 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1571 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1616 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1649 if (type && Rm == 15)
1663 if (!type && Rm == 15)
1676 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1693 if (!type && Rm == 15)
1711 if (!type && (Rt == 15 || Rm == 15))
1788 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1835 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2090 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2118 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2263 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2285 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2498 // The fixed offset encodes as Rm == 0xd, so we check for that.
2499 if (Rm == 0xd) {
2528 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2529 // variant encodes Rm == 0xf. Anything else is a register offset post-
2531 if (Rm != 0xD && Rm != 0xF &&
2532 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2610 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2664 if (Rm == 0xF)
2694 if (Rm == 0xD)
2696 else if (Rm != 0xF) {
2697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2879 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2900 if (Rm != 0xF) {
2909 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2910 // variant encodes Rm == 0xf. Anything else is a register offset post-
2912 if (Rm != 0xD && Rm != 0xF &&
2913 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2926 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2952 if (Rm != 0xF)
2959 if (Rm != 0xD && Rm != 0xF) {
2960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2974 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2983 if (Rm != 0xF) {
2992 if (Rm == 0xD)
2994 else if (Rm != 0xF) {
2995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3009 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3035 if (Rm != 0xF) {
3044 if (Rm == 0xD)
3046 else if (Rm != 0xF) {
3047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3106 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3107 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3112 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3151 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3152 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3232 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3236 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3279 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3295 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3855 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3880 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3883 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3935 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3940 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4236 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4239 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4309 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4349 if (Rm != 0xF) { // Writeback
4356 if (Rm != 0xF) {
4357 if (Rm != 0xD) {
4358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4376 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4414 if (Rm != 0xF) { // Writeback
4421 if (Rm != 0xF) {
4422 if (Rm != 0xD) {
4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4442 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4480 if (Rm != 0xF) { // Writeback
4487 if (Rm != 0xF) {
4488 if (Rm != 0xD) {
4489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4509 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4543 if (Rm != 0xF) { // Writeback
4550 if (Rm != 0xF) {
4551 if (Rm != 0xD) {
4552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4573 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4612 if (Rm != 0xF) { // Writeback
4619 if (Rm != 0xF) {
4620 if (Rm != 0xD) {
4621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4643 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4675 if (Rm != 0xF) { // Writeback
4682 if (Rm != 0xF) {
4683 if (Rm != 0xD) {
4684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4707 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4755 if (Rm != 0xF) { // Writeback
4762 if (Rm != 0xF) {
4763 if (Rm != 0xD) {
4764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4788 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4827 if (Rm != 0xF) { // Writeback
4834 if (Rm != 0xF) {
4835 if (Rm != 0xD) {
4836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4860 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4862 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4864 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4867 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4869 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4886 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4888 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4890 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4897 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4899 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5175 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5176 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5188 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
