Lines Matching refs:getOperand
79 switch (MI->getOperand(0).getImm()) {
115 const MCOperand &Dst = MI->getOperand(0);
116 const MCOperand &MO1 = MI->getOperand(1);
117 const MCOperand &MO2 = MI->getOperand(2);
118 const MCOperand &MO3 = MI->getOperand(3);
138 const MCOperand &Dst = MI->getOperand(0);
139 const MCOperand &MO1 = MI->getOperand(1);
140 const MCOperand &MO2 = MI->getOperand(2);
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
179 if (MI->getOperand(2).getReg() == ARM::SP &&
180 MI->getOperand(3).getImm() == -4) {
184 printRegName(O, MI->getOperand(1).getReg());
194 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
208 if (MI->getOperand(2).getReg() == ARM::SP &&
209 MI->getOperand(4).getImm() == 4) {
213 printRegName(O, MI->getOperand(0).getReg());
223 if (MI->getOperand(0).getReg() == ARM::SP) {
236 if (MI->getOperand(0).getReg() == ARM::SP) {
248 unsigned BaseReg = MI->getOperand(0).getReg();
250 if (MI->getOperand(i).getReg() == BaseReg)
279 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
286 NewMI.addOperand(MI->getOperand(0));
293 NewMI.addOperand(MI->getOperand(i));
303 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
304 MI->getOperand(0).getImm() == 0 &&
321 const MCOperand &Op = MI->getOperand(OpNo);
362 const MCOperand &MO1 = MI->getOperand(OpNum);
392 const MCOperand &MO1 = MI->getOperand(OpNum);
393 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
394 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
412 const MCOperand &MO1 = MI->getOperand(OpNum);
413 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
429 const MCOperand &MO1 = MI->getOperand(Op);
430 const MCOperand &MO2 = MI->getOperand(Op + 1);
431 const MCOperand &MO3 = MI->getOperand(Op + 2);
458 const MCOperand &MO1 = MI->getOperand(Op);
459 const MCOperand &MO2 = MI->getOperand(Op + 1);
470 const MCOperand &MO1 = MI->getOperand(Op);
471 const MCOperand &MO2 = MI->getOperand(Op + 1);
482 const MCOperand &MO1 = MI->getOperand(Op);
490 const MCOperand &MO3 = MI->getOperand(Op + 2);
502 const MCOperand &MO1 = MI->getOperand(OpNum);
503 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
527 const MCOperand &MO1 = MI->getOperand(Op);
528 const MCOperand &MO2 = MI->getOperand(Op + 1);
529 const MCOperand &MO3 = MI->getOperand(Op + 2);
556 const MCOperand &MO1 = MI->getOperand(Op);
562 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
572 const MCOperand &MO1 = MI->getOperand(OpNum);
573 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
590 const MCOperand &MO = MI->getOperand(OpNum);
599 const MCOperand &MO1 = MI->getOperand(OpNum);
600 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
609 const MCOperand &MO = MI->getOperand(OpNum);
619 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
627 const MCOperand &MO1 = MI->getOperand(OpNum);
628 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
650 const MCOperand &MO1 = MI->getOperand(OpNum);
651 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
664 const MCOperand &MO1 = MI->getOperand(OpNum);
674 const MCOperand &MO = MI->getOperand(OpNum);
687 const MCOperand &MO = MI->getOperand(OpNum);
699 unsigned val = MI->getOperand(OpNum).getImm();
706 unsigned val = MI->getOperand(OpNum).getImm();
713 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
727 unsigned Imm = MI->getOperand(OpNum).getImm();
737 unsigned Imm = MI->getOperand(OpNum).getImm();
752 printRegName(O, MI->getOperand(i).getReg());
760 unsigned Reg = MI->getOperand(OpNum).getReg();
769 const MCOperand &Op = MI->getOperand(OpNum);
778 const MCOperand &Op = MI->getOperand(OpNum);
784 const MCOperand &Op = MI->getOperand(OpNum);
797 const MCOperand &Op = MI->getOperand(OpNum);
946 uint32_t Banked = MI->getOperand(OpNum).getImm();
998 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1010 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1017 if (MI->getOperand(OpNum).getReg()) {
1018 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1027 O << MI->getOperand(OpNum).getImm();
1033 O << "p" << MI->getOperand(OpNum).getImm();
1039 O << "c" << MI->getOperand(OpNum).getImm();
1045 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1057 const MCOperand &MO = MI->getOperand(OpNum);
1079 O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1086 unsigned Imm = MI->getOperand(OpNum).getImm();
1095 unsigned Mask = MI->getOperand(OpNum).getImm();
1096 unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1112 const MCOperand &MO1 = MI->getOperand(Op);
1113 const MCOperand &MO2 = MI->getOperand(Op + 1);
1134 const MCOperand &MO1 = MI->getOperand(Op);
1135 const MCOperand &MO2 = MI->getOperand(Op + 1);
1185 const MCOperand &MO1 = MI->getOperand(OpNum);
1186 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1201 const MCOperand &MO1 = MI->getOperand(OpNum);
1202 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1230 const MCOperand &MO1 = MI->getOperand(OpNum);
1231 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1254 const MCOperand &MO1 = MI->getOperand(OpNum);
1255 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1284 const MCOperand &MO1 = MI->getOperand(OpNum);
1285 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1299 const MCOperand &MO1 = MI->getOperand(OpNum);
1314 const MCOperand &MO1 = MI->getOperand(OpNum);
1333 const MCOperand &MO1 = MI->getOperand(OpNum);
1334 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1335 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1355 const MCOperand &MO = MI->getOperand(OpNum);
1363 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1374 unsigned Imm = MI->getOperand(OpNum).getImm();
1381 unsigned Imm = MI->getOperand(OpNum).getImm();
1391 MCOperand Op = MI->getOperand(OpNum);
1404 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1431 O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1437 O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1444 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1451 printRegName(O, MI->getOperand(OpNum).getReg());
1458 unsigned Reg = MI->getOperand(OpNum).getReg();
1471 unsigned Reg = MI->getOperand(OpNum).getReg();
1488 printRegName(O, MI->getOperand(OpNum).getReg());
1490 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1492 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1503 printRegName(O, MI->getOperand(OpNum).getReg());
1505 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1507 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1509 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1518 printRegName(O, MI->getOperand(OpNum).getReg());
1526 unsigned Reg = MI->getOperand(OpNum).getReg();
1544 printRegName(O, MI->getOperand(OpNum).getReg());
1546 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1548 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1560 printRegName(O, MI->getOperand(OpNum).getReg());
1562 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1564 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1566 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1573 unsigned Reg = MI->getOperand(OpNum).getReg();
1590 printRegName(O, MI->getOperand(OpNum).getReg());
1592 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1594 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1605 printRegName(O, MI->getOperand(OpNum).getReg());
1607 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1609 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1611 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1623 printRegName(O, MI->getOperand(OpNum).getReg());
1625 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1627 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1638 printRegName(O, MI->getOperand(OpNum).getReg());
1640 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1644 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
