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Lines Matching refs:addReg

77     .addReg(DestReg, getDefRegState(true), SubIdx)
78     .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
96     .addReg(DestReg, getDefRegState(true), SubIdx)
97     .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
157         .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
170       MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
172       MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
309     MIB.addReg(BaseReg, RegState::Kill);
326     MIB.addReg(BaseReg).addImm(ExtraImm);
462     .addReg(ARM::R12, RegState::Define)
463     .addReg(Reg, RegState::Kill));
492     addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));