Lines Matching refs:Hexagon
1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
10 #define DEBUG_TYPE "hexagon-disassembler"
12 #include "Hexagon.h"
36 using namespace Hexagon;
41 /// \brief Hexagon disassembler for all Hexagon platforms.
284 MI.setOpcode(Hexagon::DuplexIClass0);
305 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
323 MI.getOpcode() == Hexagon::A4_ext) {
337 unsigned reg = i->getReg() - Hexagon::R0;
377 assert(Producer != Hexagon::NoRegister);
382 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
383 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
387 assert(Producer != Hexagon::NoRegister);
420 case Hexagon::S2_storerbabs:
421 opcode = Hexagon::S2_storerbgp;
423 case Hexagon::S2_storerhabs:
424 opcode = Hexagon::S2_storerhgp;
426 case Hexagon::S2_storerfabs:
427 opcode = Hexagon::S2_storerfgp;
429 case Hexagon::S2_storeriabs:
430 opcode = Hexagon::S2_storerigp;
432 case Hexagon::S2_storerbnewabs:
433 opcode = Hexagon::S2_storerbnewgp;
435 case Hexagon::S2_storerhnewabs:
436 opcode = Hexagon::S2_storerhnewgp;
438 case Hexagon::S2_storerinewabs:
439 opcode = Hexagon::S2_storerinewgp;
441 case Hexagon::S2_storerdabs:
442 opcode = Hexagon::S2_storerdgp;
444 case Hexagon::L4_loadrb_abs:
445 opcode = Hexagon::L2_loadrbgp;
447 case Hexagon::L4_loadrub_abs:
448 opcode = Hexagon::L2_loadrubgp;
450 case Hexagon::L4_loadrh_abs:
451 opcode = Hexagon::L2_loadrhgp;
453 case Hexagon::L4_loadruh_abs:
454 opcode = Hexagon::L2_loadruhgp;
456 case Hexagon::L4_loadri_abs:
457 opcode = Hexagon::L2_loadrigp;
459 case Hexagon::L4_loadrd_abs:
460 opcode = Hexagon::L2_loadrdgp;
493 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
494 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
495 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
496 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
497 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
498 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
499 Hexagon::R30, Hexagon::R31};
508 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
509 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
510 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
511 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
512 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
513 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
514 Hexagon::V30, Hexagon::V31};
523 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
524 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
525 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
526 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
535 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
536 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
537 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
538 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
546 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
547 Hexagon::P2, Hexagon::P3};
555 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
556 Hexagon::Q2, Hexagon::Q3};
565 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
566 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7,
567 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
568 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC
574 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
586 Hexagon::C1_0, Hexagon::NoRegister,
587 Hexagon::C3_2, Hexagon::NoRegister,
588 Hexagon::C7_6, Hexagon::NoRegister,
589 Hexagon::C9_8, Hexagon::NoRegister,
590 Hexagon::C11_10, Hexagon::NoRegister,
591 Hexagon::CS, Hexagon::NoRegister,
592 Hexagon::UPC, Hexagon::NoRegister
598 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
612 Register = Hexagon::M0;
615 Register = Hexagon::M1;
868 case Hexagon::S4_pstorerdf_abs:
869 case Hexagon::S4_pstorerdt_abs:
870 case Hexagon::S4_pstorerdfnew_abs:
871 case Hexagon::S4_pstorerdtnew_abs: {
885 case Hexagon::S4_pstorerbnewf_abs:
886 case Hexagon::S4_pstorerbnewt_abs:
887 case Hexagon::S4_pstorerbnewfnew_abs:
888 case Hexagon::S4_pstorerbnewtnew_abs:
889 case Hexagon::S4_pstorerhnewf_abs:
890 case Hexagon::S4_pstorerhnewt_abs:
891 case Hexagon::S4_pstorerhnewfnew_abs:
892 case Hexagon::S4_pstorerhnewtnew_abs:
893 case Hexagon::S4_pstorerinewf_abs:
894 case Hexagon::S4_pstorerinewt_abs:
895 case Hexagon::S4_pstorerinewfnew_abs:
896 case Hexagon::S4_pstorerinewtnew_abs: {
910 case Hexagon::S4_pstorerbf_abs:
911 case Hexagon::S4_pstorerbt_abs:
912 case Hexagon::S4_pstorerbfnew_abs:
913 case Hexagon::S4_pstorerbtnew_abs:
914 case Hexagon::S4_pstorerhf_abs:
915 case Hexagon::S4_pstorerht_abs:
916 case Hexagon::S4_pstorerhfnew_abs:
917 case Hexagon::S4_pstorerhtnew_abs:
918 case Hexagon::S4_pstorerif_abs:
919 case Hexagon::S4_pstorerit_abs:
920 case Hexagon::S4_pstorerifnew_abs:
921 case Hexagon::S4_pstoreritnew_abs: {
935 case Hexagon::L4_ploadrdf_abs:
936 case Hexagon::L4_ploadrdt_abs:
937 case Hexagon::L4_ploadrdfnew_abs:
938 case Hexagon::L4_ploadrdtnew_abs: {
952 case Hexagon::L4_ploadrbf_abs:
953 case Hexagon::L4_ploadrbt_abs:
954 case Hexagon::L4_ploadrbfnew_abs:
955 case Hexagon::L4_ploadrbtnew_abs:
956 case Hexagon::L4_ploadrhf_abs:
957 case Hexagon::L4_ploadrht_abs:
958 case Hexagon::L4_ploadrhfnew_abs:
959 case Hexagon::L4_ploadrhtnew_abs:
960 case Hexagon::L4_ploadrubf_abs:
961 case Hexagon::L4_ploadrubt_abs:
962 case Hexagon::L4_ploadrubfnew_abs:
963 case Hexagon::L4_ploadrubtnew_abs:
964 case Hexagon::L4_ploadruhf_abs:
965 case Hexagon::L4_ploadruht_abs:
966 case Hexagon::L4_ploadruhfnew_abs:
967 case Hexagon::L4_ploadruhtnew_abs:
968 case Hexagon::L4_ploadrif_abs:
969 case Hexagon::L4_ploadrit_abs:
970 case Hexagon::L4_ploadrifnew_abs:
971 case Hexagon::L4_ploadritnew_abs:
985 case (Hexagon::L4_loadri_abs):
988 case Hexagon::L4_loadrh_abs:
989 case Hexagon::L4_loadruh_abs:
992 case Hexagon::L4_loadrb_abs:
993 case Hexagon::L4_loadrub_abs: {
1004 case Hexagon::L4_loadrd_abs: {
1014 case Hexagon::S2_storerdabs: {
1028 case Hexagon::S2_storerinewabs:
1031 case Hexagon::S2_storerhnewabs:
1034 case Hexagon::S2_storerbnewabs: {
1047 case Hexagon::S2_storeriabs:
1050 case Hexagon::S2_storerhabs:
1051 case Hexagon::S2_storerfabs:
1054 case Hexagon::S2_storerbabs: {
1081 MI.setOpcode(Hexagon::A4_ext);
1201 op = Hexagon::V4_SL1_loadri_io;
1203 op = Hexagon::V4_SL1_loadrub_io;
1211 op = Hexagon::V4_SL2_deallocframe;
1213 op = Hexagon::V4_SL2_jumpr31;
1215 op = Hexagon::V4_SL2_jumpr31_f;
1217 op = Hexagon::V4_SL2_jumpr31_fnew;
1219 op = Hexagon::V4_SL2_jumpr31_t;
1221 op = Hexagon::V4_SL2_jumpr31_tnew;
1223 op = Hexagon::V4_SL2_loadrb_io;
1225 op = Hexagon::V4_SL2_loadrd_sp;
1227 op = Hexagon::V4_SL2_loadrh_io;
1229 op = Hexagon::V4_SL2_loadri_sp;
1231 op = Hexagon::V4_SL2_loadruh_io;
1233 op = Hexagon::V4_SL2_return;
1235 op = Hexagon::V4_SL2_return_f;
1237 op = Hexagon::V4_SL2_return_fnew;
1239 op = Hexagon::V4_SL2_return_t;
1241 op = Hexagon::V4_SL2_return_tnew;
1249 op = Hexagon::V4_SA1_addi;
1251 op = Hexagon::V4_SA1_addrx;
1253 op = Hexagon::V4_SA1_addsp;
1255 op = Hexagon::V4_SA1_and1;
1257 op = Hexagon::V4_SA1_clrf;
1259 op = Hexagon::V4_SA1_clrfnew;
1261 op = Hexagon::V4_SA1_clrt;
1263 op = Hexagon::V4_SA1_clrtnew;
1265 op = Hexagon::V4_SA1_cmpeqi;
1267 op = Hexagon::V4_SA1_combine0i;
1269 op = Hexagon::V4_SA1_combine1i;
1271 op = Hexagon::V4_SA1_combine2i;
1273 op = Hexagon::V4_SA1_combine3i;
1275 op = Hexagon::V4_SA1_combinerz;
1277 op = Hexagon::V4_SA1_combinezr;
1279 op = Hexagon::V4_SA1_dec;
1281 op = Hexagon::V4_SA1_inc;
1283 op = Hexagon::V4_SA1_seti;
1285 op = Hexagon::V4_SA1_setin1;
1287 op = Hexagon::V4_SA1_sxtb;
1289 op = Hexagon::V4_SA1_sxth;
1291 op = Hexagon::V4_SA1_tfr;
1293 op = Hexagon::V4_SA1_zxtb;
1295 op = Hexagon::V4_SA1_zxth;
1303 op = Hexagon::V4_SS1_storeb_io;
1305 op = Hexagon::V4_SS1_storew_io;
1313 op = Hexagon::V4_SS2_allocframe;
1315 op = Hexagon::V4_SS2_storebi0;
1317 op = Hexagon::V4_SS2_storebi1;
1319 op = Hexagon::V4_SS2_stored_sp;
1321 op = Hexagon::V4_SS2_storeh_io;
1323 op = Hexagon::V4_SS2_storew_sp;
1325 op = Hexagon::V4_SS2_storewi0;
1327 op = Hexagon::V4_SS2_storewi1;
1342 return Hexagon::R0 + encoded_reg;
1344 return Hexagon::R0 + encoded_reg + 8;
1347 return Hexagon::NoRegister;
1352 return Hexagon::D0 + encoded_dreg;
1354 return Hexagon::D0 + encoded_dreg + 4;
1357 return Hexagon::NoRegister;
1365 case Hexagon::V4_SL2_deallocframe:
1366 case Hexagon::V4_SL2_jumpr31:
1367 case Hexagon::V4_SL2_jumpr31_f:
1368 case Hexagon::V4_SL2_jumpr31_fnew:
1369 case Hexagon::V4_SL2_jumpr31_t:
1370 case Hexagon::V4_SL2_jumpr31_tnew:
1371 case Hexagon::V4_SL2_return:
1372 case Hexagon::V4_SL2_return_f:
1373 case Hexagon::V4_SL2_return_fnew:
1374 case Hexagon::V4_SL2_return_t:
1375 case Hexagon::V4_SL2_return_tnew:
1378 case Hexagon::V4_SS2_allocframe:
1383 case Hexagon::V4_SL1_loadri_io:
1394 case Hexagon::V4_SL1_loadrub_io:
1405 case Hexagon::V4_SL2_loadrb_io:
1416 case Hexagon::V4_SL2_loadrh_io:
1417 case Hexagon::V4_SL2_loadruh_io:
1428 case Hexagon::V4_SL2_loadrd_sp:
1436 case Hexagon::V4_SL2_loadri_sp:
1444 case Hexagon::V4_SA1_addi:
1453 case Hexagon::V4_SA1_addrx:
1462 case Hexagon::V4_SA1_and1:
1463 case Hexagon::V4_SA1_dec:
1464 case Hexagon::V4_SA1_inc:
1465 case Hexagon::V4_SA1_sxtb:
1466 case Hexagon::V4_SA1_sxth:
1467 case Hexagon::V4_SA1_tfr:
1468 case Hexagon::V4_SA1_zxtb:
1469 case Hexagon::V4_SA1_zxth:
1478 case Hexagon::V4_SA1_addsp:
1486 case Hexagon::V4_SA1_seti:
1494 case Hexagon::V4_SA1_clrf:
1495 case Hexagon::V4_SA1_clrfnew:
1496 case Hexagon::V4_SA1_clrt:
1497 case Hexagon::V4_SA1_clrtnew:
1498 case Hexagon::V4_SA1_setin1:
1504 case Hexagon::V4_SA1_cmpeqi:
1512 case Hexagon::V4_SA1_combine0i:
1513 case Hexagon::V4_SA1_combine1i:
1514 case Hexagon::V4_SA1_combine2i:
1515 case Hexagon::V4_SA1_combine3i:
1523 case Hexagon::V4_SA1_combinerz:
1524 case Hexagon::V4_SA1_combinezr:
1533 case Hexagon::V4_SS1_storeb_io:
1544 case Hexagon::V4_SS1_storew_io:
1555 case Hexagon::V4_SS2_storebi0:
1556 case Hexagon::V4_SS2_storebi1:
1564 case Hexagon::V4_SS2_storewi0:
1565 case Hexagon::V4_SS2_storewi1:
1573 case Hexagon::V4_SS2_stored_sp:
1581 case Hexagon::V4_SS2_storeh_io:
1592 case Hexagon::V4_SS2_storew_sp:
