Lines Matching refs:Hexagon
1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
42 #define DEBUG_TYPE "hexagon-lowering"
44 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
46 cl::desc("Control jump table emission on Hexagon target"));
48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
50 cl::desc("Enable Hexagon SDNode scheduling"));
100 // Implement calling convention for Hexagon.
277 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
278 Hexagon::R5
294 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
300 Hexagon::D1, Hexagon::D2
303 Hexagon::R1, Hexagon::R3
310 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
319 static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
320 Hexagon::V2, Hexagon::V3,
321 Hexagon::V4, Hexagon::V5,
322 Hexagon::V6, Hexagon::V7,
323 Hexagon::V8, Hexagon::V9,
324 Hexagon::V10, Hexagon::V11,
325 Hexagon::V12, Hexagon::V13,
326 Hexagon::V14, Hexagon::V15};
327 static const MCPhysReg VecLstD[] = { Hexagon::W0, Hexagon::W1,
328 Hexagon::W2, Hexagon::W3,
329 Hexagon::W4, Hexagon::W5,
330 Hexagon::W6, Hexagon::W7};
448 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
463 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
484 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
489 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
496 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
1048 // stack where the return value will be stored. For Hexagon, the location on
1072 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1077 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1085 RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
1092 RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
1100 RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
1107 RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
1113 RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
1547 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1548 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1549 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1550 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1551 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1552 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1553 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1554 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1555 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1556 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1557 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1560 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1561 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1566 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass);
1567 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
1568 addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
1569 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass);
1570 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
1571 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
1572 addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
1573 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
1574 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
1576 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass);
1577 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass);
1578 addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass);
1579 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass);
1580 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass);
1581 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
1582 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass);
1583 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
1584 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
1618 // Hexagon needs to optimize cases with negative constants.
1637 // Hexagon has instructions for add/sub with carry. The problem with
2080 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2149 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2269 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
2284 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2315 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2434 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
2437 Subreg = Hexagon::subreg_loreg;
2439 Subreg = Hexagon::subreg_hireg;
2441 Subreg = Hexagon::subreg_hireg;
2443 Subreg = Hexagon::subreg_hireg;
2453 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2474 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2557 unsigned OffsetReg = Hexagon::R28;
2560 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2630 case Hexagon::ALLOCA: {
2659 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2662 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2674 return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
2684 return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
2690 return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
2692 return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
2697 return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
2830 RRC = &Hexagon::VectorRegsRegClass;
2838 RRC = &Hexagon::VectorRegs128BRegClass;
2840 RRC = &Hexagon::VecDblRegsRegClass;
2846 RRC = &Hexagon::VecDblRegs128BRegClass;
