Lines Matching refs:addReg
621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
624 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
630 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
632 .addReg(P.first);
634 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
636 .addReg(P.second);
648 .addReg(AdrOp.getReg(), RSA)
715 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
724 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
744 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
746 .addReg(Op1.getReg(), RS, Op1.getSubReg())
784 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
786 .addReg(Op1.getReg(), RS, HiSR);
809 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
812 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
815 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
821 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
826 .addReg(TmpR)
827 .addReg(Op1.getReg(), RS, HiSR)
832 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
836 .addReg(TmpR)
837 .addReg(Op1.getReg(), RS, HiSR)
843 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
849 .addReg(Op1.getReg(), RS, HiSR)
855 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
858 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
861 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
866 .addReg(Op1.getReg(), RS, HiSR)
919 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
920 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
922 .addReg(Op1.getReg(), RS1, HiSR)
923 .addReg(Op2.getReg(), RS2, HiSR);
926 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
927 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
931 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
936 .addReg(Op1.getReg(), RS1, HiSR)
937 .addReg(TmpR1);
939 .addReg(TmpR2)
940 .addReg(Op2.getReg(), RS2, HiSR)
948 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
950 .addReg(Op1.getReg(), RS1, HiSR)
951 .addReg(Op2.getReg(), RS2, LoSR);
959 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
961 .addReg(Op1.getReg(), RS1, HiSR)
962 .addReg(Op2.getReg(), RS2, LoSR)
1093 .addReg(Pr.first)
1095 .addReg(Pr.second)
