Lines Matching refs:ISD
77 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
78 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
81 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
85 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
91 setOperationAction(ISD::SRA, MVT::i8, Custom);
92 setOperationAction(ISD::SHL, MVT::i8, Custom);
93 setOperationAction(ISD::SRL, MVT::i8, Custom);
94 setOperationAction(ISD::SRA, MVT::i16, Custom);
95 setOperationAction(ISD::SHL, MVT::i16, Custom);
96 setOperationAction(ISD::SRL, MVT::i16, Custom);
97 setOperationAction(ISD::ROTL, MVT::i8, Expand);
98 setOperationAction(ISD::ROTR, MVT::i8, Expand);
99 setOperationAction(ISD::ROTL, MVT::i16, Expand);
100 setOperationAction(ISD::ROTR, MVT::i16, Expand);
101 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
102 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
103 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
104 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
105 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
106 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
107 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
108 setOperationAction(ISD::SETCC, MVT::i8, Custom);
109 setOperationAction(ISD::SETCC, MVT::i16, Custom);
110 setOperationAction(ISD::SELECT, MVT::i8, Expand);
111 setOperationAction(ISD::SELECT, MVT::i16, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
113 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
114 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
115 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
118 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
119 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
120 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand);
121 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
122 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
123 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
124 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand);
125 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand);
126 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
127 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
129 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
130 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
131 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
132 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
133 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
139 setOperationAction(ISD::MUL, MVT::i8, Expand);
140 setOperationAction(ISD::MULHS, MVT::i8, Expand);
141 setOperationAction(ISD::MULHU, MVT::i8, Expand);
142 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
143 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
144 setOperationAction(ISD::MUL, MVT::i16, Expand);
145 setOperationAction(ISD::MULHS, MVT::i16, Expand);
146 setOperationAction(ISD::MULHU, MVT::i16, Expand);
147 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
148 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
150 setOperationAction(ISD::UDIV, MVT::i8, Expand);
151 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
152 setOperationAction(ISD::UREM, MVT::i8, Expand);
153 setOperationAction(ISD::SDIV, MVT::i8, Expand);
154 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
155 setOperationAction(ISD::SREM, MVT::i8, Expand);
156 setOperationAction(ISD::UDIV, MVT::i16, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
158 setOperationAction(ISD::UREM, MVT::i16, Expand);
159 setOperationAction(ISD::SDIV, MVT::i16, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
161 setOperationAction(ISD::SREM, MVT::i16, Expand);
164 setOperationAction(ISD::VASTART, MVT::Other, Custom);
165 setOperationAction(ISD::VAARG, MVT::Other, Expand);
166 setOperationAction(ISD::VAEND, MVT::Other, Expand);
167 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
168 setOperationAction(ISD::JumpTable, MVT::i16, Custom);
186 case ISD::SHL: // FALLTHROUGH
187 case ISD::SRL:
188 case ISD::SRA: return LowerShifts(Op, DAG);
189 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
190 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
191 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
192 case ISD::SETCC: return LowerSETCC(Op, DAG);
193 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
194 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
195 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
196 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
197 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
198 case ISD::VASTART: return LowerVASTART(Op, DAG);
199 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
265 const SmallVectorImpl<ISD::OutputArg> &Outs) {
270 const SmallVectorImpl<ISD::InputArg> &Ins) {
301 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
345 const SmallVectorImpl<ISD::InputArg> &Ins) {
350 const SmallVectorImpl<ISD::OutputArg> &Outs) {
369 const SmallVectorImpl<ISD::InputArg>
394 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
396 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
425 const SmallVectorImpl<ISD::InputArg>
471 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
474 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
487 ISD::ArgFlagsTy Flags = Ins[i].Flags;
523 const SmallVectorImpl<ISD::OutputArg> &Outs,
577 const SmallVectorImpl<ISD::OutputArg>
580 const SmallVectorImpl<ISD::InputArg> &Ins,
611 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
614 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
617 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
632 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
636 ISD::ArgFlagsTy Flags = Outs[i].Flags;
659 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
714 const SmallVectorImpl<ISD::InputArg> &Ins,
747 case ISD::SHL:
750 case ISD::SRA:
753 case ISD::SRL:
765 if (Opc == ISD::SRL && ShiftAmount) {
773 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
811 ISD::CondCode CC,
820 case ISD::SETEQ:
824 if (LHS.getOpcode() == ISD::Constant)
827 case ISD::SETNE:
831 if (LHS.getOpcode() == ISD::Constant)
834 case ISD::SETULE:
836 case ISD::SETUGE:
847 case ISD::SETUGT:
849 case ISD::SETULT:
860 case ISD::SETLE:
862 case ISD::SETGE:
873 case ISD::SETGT:
875 case ISD::SETLT:
895 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
921 (LHS.getOpcode() == ISD::AND ||
922 (LHS.getOpcode() == ISD::TRUNCATE &&
923 LHS.getOperand(0).getOpcode() == ISD::AND))) {
927 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
971 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
972 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
974 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
990 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1010 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1011 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1050 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1108 ISD::MemIndexedMode &AM,
1112 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1119 if (Op->getOpcode() != ISD::ADD)
1130 AM = ISD::POST_INC;
