Lines Matching refs:Mips
1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
38 #define DEBUG_TYPE "mips-asm-parser"
93 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
94 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
95 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
96 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
97 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
98 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
99 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
100 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
437 if ((TheTriple.getArch() == Triple::mips) ||
448 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
451 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
458 return getSTI().getFeatureBits()[Mips::FeatureFPXX];
462 return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
466 return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
469 return getSTI().getFeatureBits()[Mips::FeatureMips1];
472 return getSTI().getFeatureBits()[Mips::FeatureMips2];
475 return getSTI().getFeatureBits()[Mips::FeatureMips3];
478 return getSTI().getFeatureBits()[Mips::FeatureMips4];
481 return getSTI().getFeatureBits()[Mips::FeatureMips5];
484 return getSTI().getFeatureBits()[Mips::FeatureMips32];
487 return getSTI().getFeatureBits()[Mips::FeatureMips64];
490 return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
493 return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
496 return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
499 return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
502 return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
505 return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
508 return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
511 return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
515 return getSTI().getFeatureBits()[Mips::FeatureDSP];
518 return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
521 return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
524 return getSTI().getFeatureBits()[Mips::FeatureMSA];
527 return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
535 return getSTI().getFeatureBits()[Mips::FeatureMips16];
539 return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
543 return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
557 /// MipsOperand - Instances of this class represent a parsed Mips machine
587 k_PhysRegister, /// A physical register from the Mips namespace
661 unsigned ClassID = Mips::GPR32RegClassID;
669 unsigned ClassID = Mips::GPR32RegClassID;
677 unsigned ClassID = Mips::GPR64RegClassID;
688 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
696 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
704 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
712 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
720 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
730 unsigned ClassID = Mips::MSA128BRegClassID;
738 unsigned ClassID = Mips::MSACtrlRegClassID;
746 unsigned ClassID = Mips::COP0RegClassID;
754 unsigned ClassID = Mips::COP2RegClassID;
762 unsigned ClassID = Mips::COP3RegClassID;
770 unsigned ClassID = Mips::ACC64DSPRegClassID;
778 unsigned ClassID = Mips::HI32DSPRegClassID;
786 unsigned ClassID = Mips::LO32DSPRegClassID;
794 unsigned ClassID = Mips::CCRRegClassID;
802 unsigned ClassID = Mips::HWRegsRegClassID;
1031 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
1036 && (getMemBase()->getGPR32Reg() == Mips::SP);
1053 if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
1054 (R0 == Mips::S0_64 && R1 == Mips::RA_64)))
1082 if ((R0 == Mips::A1 && R1 == Mips::A2) ||
1083 (R0 == Mips::A1 && R1 == Mips::A3) ||
1084 (R0 == Mips::A2 && R1 == Mips::A3) ||
1085 (R0 == Mips::A0 && R1 == Mips::S5) ||
1086 (R0 == Mips::A0 && R1 == Mips::S6) ||
1087 (R0 == Mips::A0 && R1 == Mips::A1) ||
1088 (R0 == Mips::A0 && R1 == Mips::A2) ||
1089 (R0 == Mips::A0 && R1 == Mips::A3))
1388 case Mips::JALS_MM:
1389 case Mips::JALRS_MM:
1390 case Mips::JALRS16_MM:
1391 case Mips::BGEZALS_MM:
1392 case Mips::BLTZALS_MM:
1503 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc,
1508 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, Instructions);
1526 case Mips::BBIT0:
1527 case Mips::BBIT032:
1528 case Mips::BBIT1:
1529 case Mips::BBIT132:
1533 case Mips::BEQ:
1534 case Mips::BNE:
1535 case Mips::BEQ_MM:
1536 case Mips::BNE_MM:
1547 case Mips::BGEZ:
1548 case Mips::BGTZ:
1549 case Mips::BLEZ:
1550 case Mips::BLTZ:
1551 case Mips::BGEZAL:
1552 case Mips::BLTZAL:
1553 case Mips::BC1F:
1554 case Mips::BC1T:
1555 case Mips::BGEZ_MM:
1556 case Mips::BGTZ_MM:
1557 case Mips::BLEZ_MM:
1558 case Mips::BLTZ_MM:
1559 case Mips::BGEZAL_MM:
1560 case Mips::BLTZAL_MM:
1561 case Mips::BC1F_MM:
1562 case Mips::BC1T_MM:
1573 case Mips::BEQZ16_MM:
1574 case Mips::BEQZC16_MMR6:
1575 case Mips::BNEZ16_MM:
1576 case Mips::BNEZC16_MMR6:
1591 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
1606 case Mips::BBIT0:
1607 case Mips::BBIT032:
1608 case Mips::BBIT1:
1609 case Mips::BBIT132:
1616 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
1617 Opcode == Mips::BBIT1 ? 63 : 31))
1620 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
1621 : Mips::BBIT132);
1626 case Mips::SEQi:
1627 case Mips::SNEi:
1641 if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
1672 emitRRX(Mips::LW, Mips::T9, Mips::GP,
1674 emitRRX(Mips::ADDiu, Mips::T9, Mips::T9,
1684 emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1694 emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1700 JalrInst.setOpcode(Mips::JALRS_MM);
1702 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
1703 JalrInst.addOperand(MCOperand::createReg(Mips::RA));
1704 JalrInst.addOperand(MCOperand::createReg(Mips::T9));
1762 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
1763 (BaseReg.getReg() == Mips::GP ||
1764 BaseReg.getReg() == Mips::GP_64)) {
1766 emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
1783 case Mips::ADDIUS5_MM:
1791 case Mips::ADDIUSP_MM:
1800 case Mips::SLL16_MM:
1801 case Mips::SRL16_MM:
1809 case Mips::LI16_MM:
1817 case Mips::ADDIUR2_MM:
1826 case Mips::ADDIUR1SP_MM:
1836 case Mips::ANDI16_MM:
1846 case Mips::LBU16_MM:
1854 case Mips::TEQ_MM:
1855 case Mips::TGE_MM:
1856 case Mips::TGEU_MM:
1857 case Mips::TLT_MM:
1858 case Mips::TLTU_MM:
1859 case Mips::TNE_MM:
1860 case Mips::SB16_MM:
1861 case Mips::SB16_MMR6:
1869 case Mips::LHU16_MM:
1870 case Mips::SH16_MM:
1871 case Mips::SH16_MMR6:
1879 case Mips::LW16_MM:
1880 case Mips::SW16_MM:
1881 case Mips::SW16_MMR6:
1889 case Mips::ADDIUPC_MM:
1917 if ((Inst.getOpcode() == Mips::JalOneReg ||
1918 Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&
1948 case Mips::LoadImm32:
1951 case Mips::LoadImm64:
1954 case Mips::LoadAddrImm32:
1955 case Mips::LoadAddrImm64:
1960 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
1962 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
1966 case Mips::LoadAddrReg32:
1967 case Mips::LoadAddrReg64:
1975 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
1979 case Mips::B_MM_Pseudo:
1980 case Mips::B_MMR6_Pseudo:
1983 case Mips::SWM_MM:
1984 case Mips::LWM_MM:
1987 case Mips::JalOneReg:
1988 case Mips::JalTwoReg:
1991 case Mips::BneImm:
1992 case Mips::BeqImm:
1994 case Mips::BLT:
1995 case Mips::BLE:
1996 case Mips::BGE:
1997 case Mips::BGT:
1998 case Mips::BLTU:
1999 case Mips::BLEU:
2000 case Mips::BGEU:
2001 case Mips::BGTU:
2002 case Mips::BLTL:
2003 case Mips::BLEL:
2004 case Mips::BGEL:
2005 case Mips::BGTL:
2006 case Mips::BLTUL:
2007 case Mips::BLEUL:
2008 case Mips::BGEUL:
2009 case Mips::BGTUL:
2010 case Mips::BLTImmMacro:
2011 case Mips::BLEImmMacro:
2012 case Mips::BGEImmMacro:
2013 case Mips::BGTImmMacro:
2014 case Mips::BLTUImmMacro:
2015 case Mips::BLEUImmMacro:
2016 case Mips::BGEUImmMacro:
2017 case Mips::BGTUImmMacro:
2018 case Mips::BLTLImmMacro:
2019 case Mips::BLELImmMacro:
2020 case Mips::BGELImmMacro:
2021 case Mips::BGTLImmMacro:
2022 case Mips::BLTULImmMacro:
2023 case Mips::BLEULImmMacro:
2024 case Mips::BGEULImmMacro:
2025 case Mips::BGTULImmMacro:
2028 case Mips::SDivMacro:
2031 case Mips::DSDivMacro:
2034 case Mips::UDivMacro:
2037 case Mips::DUDivMacro:
2040 case Mips::Ulh:
2042 case Mips::Ulhu:
2044 case Mips::Ulw:
2046 case Mips::NORImm:
2049 case Mips::ADDi:
2050 case Mips::ADDiu:
2051 case Mips::SLTi:
2052 case Mips::SLTiu:
2062 case Mips::ANDi:
2063 case Mips::ORi:
2064 case Mips::XORi:
2074 case Mips::ROL:
2075 case Mips::ROR:
2078 case Mips::ROLImm:
2079 case Mips::RORImm:
2082 case Mips::DROL:
2083 case Mips::DROR:
2086 case Mips::DROLImm:
2087 case Mips::DRORImm:
2101 if (Opcode == Mips::JalOneReg) {
2104 JalrInst.setOpcode(Mips::JALRS16_MM);
2107 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM);
2110 JalrInst.setOpcode(Mips::JALR);
2111 JalrInst.addOperand(MCOperand::createReg(Mips::RA));
2114 } else if (Opcode == Mips::JalTwoReg) {
2117 JalrInst.setOpcode(Mips::JALRS_MM);
2119 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
2147 /// @param SrcReg A register to add to the immediate or Mips::NoRegister
2176 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
2179 if (SrcReg != Mips::NoRegister)
2200 emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, Instructions);
2204 emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, Instructions);
2216 emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, Instructions);
2232 emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, Instructions);
2233 emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, Instructions);
2241 emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, Instructions);
2242 emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, Instructions);
2244 emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Instructions);
2250 emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, Instructions);
2252 emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Instructions);
2270 emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, Instructions);
2271 emitRRI(Mips
2286 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
2299 emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, Instructions);
2325 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
2371 bool UseSrcReg = SrcReg != Mips::NoRegister;
2395 emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
2397 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HigherExpr),
2399 emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Instructions);
2400 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), IDLoc,
2402 emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Instructions);
2403 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), IDLoc,
2405 emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, Instructions);
2418 emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
2420 emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc,
2422 emitRRX(Mips::DADDiu, DstReg, DstReg, MCOperand::createExpr(HigherExpr),
2424 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), IDLoc,
2426 emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, Instructions);
2427 emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, Instructions);
2429 emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, Instructions);
2453 emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, Instructions);
2454 emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), IDLoc,
2458 emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Instructions);
2473 Inst.setOpcode(Mips::BEQ_MM);
2474 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
2475 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
2483 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
2490 Inst.setOpcode(Mips::BEQ_MM);
2491 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
2492 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
2520 case Mips::BneImm:
2521 OpCode = Mips::BNE;
2523 case Mips::BeqImm:
2524 OpCode = Mips::BEQ;
2533 emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
2542 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
2600 bool IsGPR = (RegClassIDOp0 == Mips::GPR32RegClassID) ||
2601 (RegClassIDOp0 == Mips::GPR64RegClassID);
2612 emitRX(Mips::LUi, TmpRegNum,
2617 if (BaseRegNum != Mips::ZERO)
2618 emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, Instructions);
2633 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;
2641 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
2642 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
2643 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
2644 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
2647 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
2649 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
2682 case Mips::BLTImmMacro:
2683 PseudoOpcode = Mips::BLT;
2685 case Mips::BLEImmMacro:
2686 PseudoOpcode = Mips::BLE;
2688 case Mips::BGEImmMacro:
2689 PseudoOpcode = Mips::BGE;
2691 case Mips::BGTImmMacro:
2692 PseudoOpcode = Mips::BGT;
2694 case Mips::BLTUImmMacro:
2695 PseudoOpcode = Mips::BLTU;
2697 case Mips::BLEUImmMacro:
2698 PseudoOpcode = Mips::BLEU;
2700 case Mips::BGEUImmMacro:
2701 PseudoOpcode = Mips::BGEU;
2703 case Mips::BGTUImmMacro:
2704 PseudoOpcode = Mips::BGTU;
2706 case Mips::BLTLImmMacro:
2707 PseudoOpcode = Mips::BLTL;
2709 case Mips::BLELImmMacro:
2710 PseudoOpcode = Mips::BLEL;
2712 case Mips::BGELImmMacro:
2713 PseudoOpcode = Mips::BGEL;
2715 case Mips::BGTLImmMacro:
2716 PseudoOpcode = Mips::BGTL;
2718 case Mips::BLTULImmMacro:
2719 PseudoOpcode = Mips::BLTUL;
2721 case Mips::BLEULImmMacro:
2722 PseudoOpcode = Mips::BLEUL;
2724 case Mips::BGEULImmMacro:
2725 PseudoOpcode = Mips::BGEUL;
2727 case Mips::BGTULImmMacro:
2728 PseudoOpcode = Mips::BGTUL;
2732 if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
2738 case Mips::BLT:
2739 case Mips::BLTU:
2740 case Mips::BLTL:
2741 case Mips::BLTUL:
2744 IsUnsigned = ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
2745 IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
2746 ZeroSrcOpcode = Mips::BGTZ;
2747 ZeroTrgOpcode = Mips::BLTZ;
2749 case Mips::BLE:
2750 case Mips::BLEU:
2751 case Mips::BLEL:
2752 case Mips::BLEUL:
2755 IsUnsigned = ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
2756 IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
2757 ZeroSrcOpcode = Mips::BGEZ;
2758 ZeroTrgOpcode = Mips::BLEZ;
2760 case Mips::BGE:
2761 case Mips::BGEU:
2762 case Mips::BGEL:
2763 case Mips::BGEUL:
2766 IsUnsigned = ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
2767 IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
2768 ZeroSrcOpcode = Mips::BLEZ;
2769 ZeroTrgOpcode = Mips::BGEZ;
2771 case Mips::BGT:
2772 case Mips::BGTU:
2773 case Mips::BGTL:
2774 case Mips::BGTUL:
2777 IsUnsigned = ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
2778 IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
2779 ZeroSrcOpcode = Mips::BLTZ;
2780 ZeroTrgOpcode = Mips::BGTZ;
2786 bool IsTrgRegZero = (TrgReg == Mips::ZERO);
2787 bool IsSrcRegZero = (SrcReg == Mips::ZERO);
2792 if (PseudoOpcode == Mips::BLT) {
2793 emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2797 if (PseudoOpcode == Mips::BLE) {
2798 emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2803 if (PseudoOpcode == Mips::BGE) {
2804 emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2809 if (PseudoOpcode == Mips::BGT) {
2810 emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2814 if (PseudoOpcode == Mips::BGTU) {
2815 emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
2822 emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2832 if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) ||
2833 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) {
2840 if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) ||
2841 (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) {
2847 emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2865 emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
2866 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
2903 emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
2907 emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
2908 : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
2909 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2935 DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
2936 ZeroReg = Mips::ZERO_64;
2938 DivOp = Signed ? Mips::SDIV : Mips::UDIV;
2939 ZeroReg = Mips::ZERO;
2944 if (RsReg == Mips::ZERO || RsReg == Mips::ZERO_64) {
2945 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)
2948 if (Signed && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
2950 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions);
2954 emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions);
2963 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
2967 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions);
2971 emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions);
2983 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions);
2988 emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc,
2995 emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions);
2998 emitR(Mips::MFLO, RsReg, IDLoc, Instructions);
3006 emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Instructions);
3009 emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Instructions);
3010 emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, Instructions);
3011 emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, Instructions);
3014 emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Instructions);
3015 emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, Instructions);
3019 emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Instructions);
3022 emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions);
3023 emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions);
3024 emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions);
3026 emitR(Mips::MFLO, RsReg, IDLoc, Instructions);
3065 if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(),
3075 if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
3094 emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
3097 emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc,
3100 emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, Instructions);
3102 emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, Instructions);
3139 if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(),
3149 if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
3163 emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc,
3166 emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset, IDLoc,
3180 unsigned ATReg = Mips::NoRegister;
3181 unsigned FinalDstReg = Mips::NoRegister;
3198 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, Inst.getLoc(), Instructions)) {
3202 case (Mips::ADDi):
3203 FinalOpcode = Mips::ADD;
3205 case (Mips::ADDiu):
3206 FinalOpcode = Mips::ADDu;
3208 case (Mips::ANDi):
3209 FinalOpcode = Mips::AND;
3211 case (Mips::NORImm):
3212 FinalOpcode = Mips::NOR;
3214 case (Mips::ORi):
3215 FinalOpcode = Mips::OR;
3217 case (Mips::SLTi):
3218 FinalOpcode = Mips::SLT;
3220 case (Mips::SLTiu):
3221 FinalOpcode = Mips::SLTu;
3223 case (Mips::XORi):
3224 FinalOpcode = Mips::XOR;
3228 if (FinalDstReg == Mips::NoRegister)
3240 unsigned ATReg = Mips::NoRegister;
3246 unsigned FirstShift = Mips::NOP;
3247 unsigned SecondShift = Mips::NOP;
3257 if (Inst.getOpcode() == Mips::ROL) {
3258 emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3259 emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Instructions);
3263 if (Inst.getOpcode() == Mips::ROR) {
3264 emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3276 case Mips::ROL:
3277 FirstShift = Mips::SRLV;
3278 SecondShift = Mips::SLLV;
3280 case Mips::ROR:
3281 FirstShift = Mips::SLLV;
3282 SecondShift = Mips::SRLV;
3290 emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3293 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions);
3304 unsigned ATReg = Mips::NoRegister;
3309 unsigned FirstShift = Mips::NOP;
3310 unsigned SecondShift = Mips::NOP;
3314 if (Inst.getOpcode() == Mips::ROLImm) {
3319 emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), Instructions);
3323 if (Inst.getOpcode() == Mips::RORImm) {
3324 emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), Instructions);
3334 emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), Instructions);
3341 case Mips::ROLImm:
3342 FirstShift = Mips::SLL;
3343 SecondShift = Mips::SRL;
3345 case Mips::RORImm:
3346 FirstShift = Mips::SRL;
3347 SecondShift = Mips::SLL;
3357 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions);
3368 unsigned ATReg = Mips::NoRegister;
3374 unsigned FirstShift = Mips::NOP;
3375 unsigned SecondShift = Mips::NOP;
3385 if (Inst.getOpcode() == Mips::DROL) {
3386 emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3387 emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Instructions);
3391 if (Inst.getOpcode() == Mips::DROR) {
3392 emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), Instructions);
3404 case Mips::DROL:
3405 FirstShift = Mips::DSRLV;
3406 SecondShift = Mips::DSLLV;
3408 case Mips::DROR:
3409 FirstShift = Mips::DSLLV;
3410 SecondShift = Mips::DSRLV;
3418 emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Instructions);
3421 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions);
3432 unsigned ATReg = Mips::NoRegister;
3437 unsigned FirstShift = Mips::NOP;
3438 unsigned SecondShift = Mips::NOP;
3444 unsigned FinalOpcode = Mips::NOP;
3446 FinalOpcode = Mips::DROTR;
3448 FinalOpcode = Mips::DROTR32;
3450 if (Inst.getOpcode() == Mips::DROLImm)
3451 FinalOpcode = Mips::DROTR32;
3453 FinalOpcode = Mips::DROTR;
3455 if (Inst.getOpcode() == Mips::DROLImm)
3456 FinalOpcode = Mips::DROTR;
3458 FinalOpcode = Mips::DROTR32;
3462 if (Inst.getOpcode() == Mips::DROLImm)
3473 emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), Instructions);
3480 case Mips::DROLImm:
3482 FirstShift = Mips::DSLL;
3483 SecondShift = Mips::DSRL32;
3486 FirstShift = Mips::DSLL32;
3487 SecondShift = Mips::DSRL32;
3490 FirstShift = Mips::DSLL32;
3491 SecondShift = Mips::DSRL;
3494 case Mips::DRORImm:
3496 FirstShift = Mips::DSRL;
3497 SecondShift = Mips::DSLL32;
3500 FirstShift = Mips::DSRL32;
3501 SecondShift = Mips::DSLL32;
3504 FirstShift = Mips::DSRL32;
3505 SecondShift = Mips::DSLL;
3516 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions);
3527 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Instructions);
3529 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Instructions);
3535 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
3545 MemInst.setOpcode(IsLoad ? Mips::LW : Mips::SW);
3546 MemInst.addOperand(MCOperand::createReg(Mips::GP));
3547 MemInst.addOperand(MCOperand::createReg(Mips::SP));
3553 emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc,
3562 if (Opcode == Mips::JALR_HB &&
3866 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex);
3875 return getReg(isGP64bit() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
4486 unsigned PrevReg = Mips::NoRegister;
4501 if ((isGP64bit() && RegNo == Mips::RA_64) ||
4502 (!isGP64bit() && RegNo == Mips::RA)) {
4507 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) ||
4508 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) &&
4521 if ((PrevReg == Mips::NoRegister) &&
4522 ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) ||
4523 (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) {
4526 } else if (!(((RegNo == Mips::FP || RegNo == Mips::RA ||
4527 (RegNo >= Mips::S0 && RegNo <= Mips::S7)) &&
4529 ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 ||
4530 (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) &&
4534 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
4535 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) ||
4536 (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 &&
4932 setFeatureBits(Mips::FeatureMSA, "msa");
4945 clearFeatureBits(Mips::FeatureMSA, "msa");
4960 clearFeatureBits(Mips::FeatureDSP, "dsp");
4975 setFeatureBits(Mips::FeatureMips16, "mips16");
4991 clearFeatureBits(Mips::FeatureMips16, "mips16");
5033 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
5047 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
5095 setFeatureBits(Mips::FeatureSoftFloat, "soft-float");
5106 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float");
5198 case Mips::FeatureDSP:
5199 setFeatureBits(Mips::FeatureDSP, "dsp");
5202 case Mips::FeatureMicroMips:
5205 case Mips::FeatureMips1:
5209 case Mips::FeatureMips2:
5213 case Mips::FeatureMips3:
5217 case Mips::FeatureMips4:
5221 case Mips::FeatureMips5:
5225 case Mips::FeatureMips32:
5229 case Mips::FeatureMips32r2:
5233 case Mips::FeatureMips32r3:
5237 case Mips::FeatureMips32r5:
5241 case Mips::FeatureMips32r6:
5245 case Mips::FeatureMips64:
5249 case Mips::FeatureMips64r2:
5253 case Mips::FeatureMips64r3:
5257 case Mips::FeatureMips64r5:
5261 case Mips::FeatureMips64r6:
5509 return parseSetFeature(Mips::FeatureMicroMips);
5513 return parseSetFeature(Mips::FeatureMips1);
5515 return parseSetFeature(Mips::FeatureMips2);
5517 return parseSetFeature(Mips::FeatureMips3);
5519 return parseSetFeature(Mips::FeatureMips4);
5521 return parseSetFeature(Mips::FeatureMips5);
5523 return parseSetFeature(Mips::FeatureMips32);
5525 return parseSetFeature(Mips::FeatureMips32r2);
5527 return parseSetFeature(Mips::FeatureMips32r3);
5529 return parseSetFeature(Mips::FeatureMips32r5);
5531 return parseSetFeature(Mips::FeatureMips32r6);
5533 return parseSetFeature(Mips::FeatureMips64);
5535 return parseSetFeature(Mips::FeatureMips64r2);
5537 return parseSetFeature(Mips::FeatureMips64r3);
5539 return parseSetFeature(Mips::FeatureMips64r5);
5541 return parseSetFeature(Mips::FeatureMips64r6);
5543 return parseSetFeature(Mips::FeatureDSP);
5713 clearModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
5720 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
5737 setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
5744 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
5758 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float");
5765 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
5777 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float");
5784 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
5828 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
5858 setModuleFeatureBits(Mips::FeatureFPXX, "fpxx");
5859 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64");
5861 setFeatureBits(Mips::FeatureFPXX, "fpxx");
5862 clearFeatureBits(Mips::FeatureFP64Bit, "fp64");
5884 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx");
5885 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64");
5887 clearFeatureBits(Mips::FeatureFPXX, "fpxx");
5888 clearFeatureBits(Mips::FeatureFP64Bit, "fp64");
5893 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx");
5894 setModuleFeatureBits(Mips::FeatureFP64Bit, "fp64");
5896 clearFeatureBits(Mips::FeatureFPXX, "fpxx");
5897 setFeatureBits(Mips::FeatureFP64Bit, "fp64");
