Lines Matching refs:OpNo
221 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
225 const MCOperand &MO = MI.getOperand(OpNo);
244 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
248 const MCOperand &MO = MI.getOperand(OpNo);
266 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
270 const MCOperand &MO = MI.getOperand(OpNo);
288 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
292 const MCOperand &MO = MI.getOperand(OpNo);
311 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
315 const MCOperand &MO = MI.getOperand(OpNo);
334 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
338 const MCOperand &MO = MI.getOperand(OpNo);
357 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
360 const MCOperand &MO = MI.getOperand(OpNo);
374 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
378 const MCOperand &MO = MI.getOperand(OpNo);
393 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
397 const MCOperand &MO = MI.getOperand(OpNo);
411 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
415 const MCOperand &MO = MI.getOperand(OpNo);
429 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
433 const MCOperand &MO = MI.getOperand(OpNo);
448 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
452 const MCOperand &MO = MI.getOperand(OpNo);
462 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
466 const MCOperand &MO = MI.getOperand(OpNo);
476 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
480 const MCOperand &MO = MI.getOperand(OpNo);
666 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
670 assert(MI.getOperand(OpNo).isReg());
671 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
672 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
710 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
714 assert(MI.getOperand(OpNo).isReg());
715 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
716 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
722 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
726 assert(MI.getOperand(OpNo).isReg());
727 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
729 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
736 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
740 assert(MI.getOperand(OpNo).isReg());
741 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
743 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
750 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
754 assert(MI.getOperand(OpNo).isReg());
755 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
757 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
764 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
768 assert(MI.getOperand(OpNo).isReg() &&
769 (MI.getOperand(OpNo).getReg() == Mips::SP ||
770 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
772 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
779 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
783 assert(MI.getOperand(OpNo).isReg() &&
784 MI.getOperand(OpNo).getReg() == Mips::GP &&
787 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
794 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
798 assert(MI.getOperand(OpNo).isReg());
799 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
801 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
807 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
817 OpNo = MI.getNumOperands() - 2;
822 assert(MI.getOperand(OpNo).isReg());
823 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
824 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
830 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
834 assert(MI.getOperand(OpNo).isReg());
835 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
837 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
843 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
855 OpNo = MI.getNumOperands() - 2;
860 assert(MI.getOperand(OpNo).isReg());
862 assert(MI.getOperand(OpNo+1).isImm());
863 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
871 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
874 assert(MI.getOperand(OpNo-1).isImm());
875 assert(MI.getOperand(OpNo).isImm());
876 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
877 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
884 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
887 assert(MI.getOperand(OpNo).isImm());
888 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
894 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
897 const MCOperand &MO = MI.getOperand(OpNo);
915 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
918 const MCOperand &MO = MI.getOperand(OpNo);
921 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
936 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
939 assert(MI.getOperand(OpNo).isImm());
940 const MCOperand &MO = MI.getOperand(OpNo);
945 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
948 assert(MI.getOperand(OpNo).isImm());
949 const MCOperand &MO = MI.getOperand(OpNo);
973 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
981 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
993 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1000 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
1003 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1007 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1041 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1044 const MCOperand &MO = MI.getOperand(OpNo);
