Lines Matching refs:Mips
1 //===-- MipsastISel.cpp - Mips FastISel implementation
241 Opc = Mips::AND;
244 Opc = Mips::OR;
247 Opc = Mips::XOR;
265 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
284 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
285 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
298 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
308 unsigned Opc = Mips::ADDiu;
309 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
312 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
320 emitInst(Mips::LUi, TmpReg).addImm(Hi);
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
323 emitInst(Mips::LUi, ResultReg).addImm(Hi);
333 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
335 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
339 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
341 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
343 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
344 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
361 emitInst(Mips::LW, DestReg)
367 emitInst(Mips::ADDiu, TempReg)
376 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
378 emitInst(Mips::LW, DestReg)
596 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
597 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
598 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
602 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
603 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
604 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
608 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
612 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
616 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
617 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
618 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
622 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
623 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
624 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
628 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
632 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
636 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
637 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
642 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
643 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
644 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
662 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
663 CondMovOpc = Mips::MOVT_I;
666 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
667 CondMovOpc = Mips::MOVF_I;
670 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
671 CondMovOpc = Mips::MOVT_I;
674 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
675 CondMovOpc = Mips::MOVT_I;
678 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
679 CondMovOpc = Mips::MOVF_I;
682 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
683 CondMovOpc = Mips::MOVF_I;
688 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
689 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
690 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
691 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
693 Mips::FCC0, RegState::ImplicitDefine);
696 .addReg(Mips::FCC0)
712 ResultReg = createResultReg(&Mips::GPR32RegClass);
713 Opc = Mips::LW;
717 ResultReg = createResultReg(&Mips::GPR32RegClass);
718 Opc = Mips::LHu;
722 ResultReg = createResultReg(&Mips::GPR32RegClass);
723 Opc = Mips::LBu;
729 ResultReg = createResultReg(&Mips::FGR32RegClass);
730 Opc = Mips::LWC1;
736 ResultReg = createResultReg(&Mips::AFGR64RegClass);
737 Opc = Mips::LDC1;
773 Opc = Mips::SB;
776 Opc = Mips::SH;
779 Opc = Mips::SW;
784 Opc = Mips::SWC1;
789 Opc = Mips::SDC1;
913 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
916 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
927 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
951 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
952 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
968 CondMovOpc = Mips::MOVN_I_I;
969 RC = &Mips::GPR32RegClass;
971 CondMovOpc = Mips::MOVN_I_S;
972 RC = &Mips::FGR32RegClass;
974 CondMovOpc = Mips::MOVN_I_D32;
975 RC = &Mips::AFGR64RegClass;
988 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1023 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1027 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1061 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1062 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1063 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1067 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1086 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1097 VA.convertToReg(Mips::F12);
1099 VA.convertToReg(Mips::D6);
1104 VA.convertToReg(Mips::F14);
1106 VA.convertToReg(Mips::D7);
1115 VA.convertToReg(Mips::A0);
1118 VA.convertToReg(Mips::A1);
1121 VA.convertToReg(Mips::A2);
1124 VA.convertToReg(Mips::A3);
1165 llvm_unreachable("Mips does not use custom args.");
1170 // from the AArch64 port and should be essentially fine for Mips too.
1191 Addr.setReg(Mips::SP);
1210 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1307 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1309 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1310 Mips::RA).addReg(Mips::T9);
1343 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1348 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1354 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1358 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1359 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1360 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1361 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1367 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1368 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1369 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1375 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1380 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1381 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1382 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1383 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1385 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1386 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1388 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1389 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1390 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1506 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1555 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1575 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1576 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1577 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1587 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1590 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1623 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1643 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1663 DivOpc = Mips::SDIV;
1667 DivOpc = Mips::UDIV;
1677 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1679 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1684 ? Mips::MFHI
1685 : Mips::MFLO;
1698 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1710 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1729 Opcode = Mips::SLL;
1732 Opcode = Mips::SRA;
1735 Opcode = Mips::SRL;
1752 Opcode = Mips::SLLV;
1755 Opcode = Mips::SRAV;
1758 Opcode = Mips::SRLV;
1834 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1845 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1846 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1847 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1863 if (MachineInstOpcode == Mips::MUL) {
1871 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1872 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1881 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
