Lines Matching refs:addReg
158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
269 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
309 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
312 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
344 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
362 .addReg(MFI->getGlobalBaseReg())
368 .addReg(DestReg)
379 .addReg(MFI->getGlobalBaseReg())
597 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
598 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
603 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
604 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
608 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
612 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
617 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
618 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
623 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
624 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
628 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
632 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
637 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
643 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
644 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
690 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
691 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
692 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
695 .addReg(RegWithOne)
696 .addReg(Mips::FCC0)
697 .addReg(RegWithZero, RegState::Implicit);
808 .addReg(SrcReg)
917 .addReg(CondReg)
952 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1001 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1003 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1027 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1066 emitInst(Opc, TempReg).addReg(SrcReg);
1067 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1162 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1230 ResultReg).addReg(RVLocs[0].getLocReg());
1307 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1310 Mips::RA).addReg(Mips::T9);
1314 MIB.addReg(Reg, RegState::Implicit);
1348 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1358 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1359 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1360 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1361 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1368 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1369 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1380 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1381 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1382 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1383 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1385 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1386 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1388 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1389 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1390 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1501 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1508 MIB.addReg(RetRegs[i], RegState::Implicit);
1576 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1577 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1587 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1590 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1623 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1676 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1677 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1739 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1762 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1847 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1869 .addReg(Op0, getKillRegState(Op0IsKill))
1870 .addReg(Op1, getKillRegState(Op1IsKill))
1871 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1872 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
