Lines Matching defs:ShiftAmt
1190 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1231 // sll shiftamt,ptrlsb2,3
1233 // sll mask,maskupper,shiftamt
1235 // sll incr2,incr,shiftamt
1244 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1249 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1254 .addReg(MaskUpper).addReg(ShiftAmt);
1256 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1310 // srl srlres,maskedoldval1,shiftamt
1317 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1428 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1474 // sll shiftamt,ptrlsb2,3
1476 // sll mask,maskupper,shiftamt
1479 // sll shiftedcmpval,maskedcmpval,shiftamt
1481 // sll shiftednewval,maskednewval,shiftamt
1489 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1494 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1499 .addReg(MaskUpper).addReg(ShiftAmt);
1504 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1508 .addReg(MaskedNewVal).addReg(ShiftAmt);
1539 // srl srlres,maskedoldval0,shiftamt
1544 .addReg(MaskedOldVal0).addReg(ShiftAmt);
