Lines Matching refs:Mips
16 #include "Mips.h"
33 #define DEBUG_TYPE "mips-long-branch"
38 "skip-mips-long-branch",
40 cl::desc("MIPS: Skip long branch pass."),
44 "force-mips-long-branch",
46 cl::desc("MIPS: Expand all branches to long format."),
71 return "Mips Long Branch";
276 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
296 .addReg(Mips::SP).addImm(-8);
297 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
298 .addReg(Mips::SP).addImm(0);
316 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
320 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
321 .addReg(Mips::AT)
327 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
328 .addReg(Mips::RA).addReg(Mips::AT);
329 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
330 .addReg(Mips::SP).addImm(0);
334 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
335 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
336 .addReg(Mips::SP).addImm(8));
339 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
340 .addReg(Mips::SP).addImm(8);
343 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
344 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
382 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
383 .addReg(Mips::SP_64).addImm(-16);
384 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
385 .addReg(Mips::SP_64).addImm(0);
386 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
387 Mips::AT_64).addReg(Mips::ZERO_64)
389 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
390 .addReg(Mips::AT_64).addImm(16);
395 BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
396 .addReg(Mips::AT_64)
402 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
403 .addReg(Mips::RA_64).addReg(Mips::AT_64);
404 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
405 .addReg(Mips::SP_64).addImm(0);
408 .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
409 .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
410 .addReg(Mips::SP_64).addImm(16));
423 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
424 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
443 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
445 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
446 .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
447 MBB.removeLiveIn(Mips::V0);
