Lines Matching refs:Mips
38 if (Mips::ACC64RegClass.contains(Src))
39 return std::make_pair((unsigned)Mips::PseudoMFHI,
40 (unsigned)Mips::PseudoMFLO);
42 if (Mips::ACC64DSPRegClass.contains(Src))
43 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
45 if (Mips::ACC128RegClass.contains(Src))
46 return std::make_pair((unsigned)Mips::PseudoMFHI64,
47 (unsigned)Mips::PseudoMFLO64);
100 case Mips::LOAD_CCOND_DSP:
103 case Mips::STORE_CCOND_DSP:
106 case Mips::LOAD_ACC64:
107 case Mips::LOAD_ACC64DSP:
110 case Mips::LOAD_ACC128:
113 case Mips::STORE_ACC64:
114 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
116 case Mips::STORE_ACC64DSP:
117 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
119 case Mips::STORE_ACC128:
120 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
122 case Mips::BuildPairF64:
126 case Mips::BuildPairF64_64:
130 case Mips::ExtractElementF64:
134 case Mips::ExtractElementF64_64:
193 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
194 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
250 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
251 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
289 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
295 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
297 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
328 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
352 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
359 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
360 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
395 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
398 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
439 if (Mips::AFGR64RegClass.contains(Reg)) {
441 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
443 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
457 } else if (Mips::FGR64RegClass.contains(Reg)) {
528 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
546 // hazards. Pre R2 Mips relies on an implementation defined number
560 "static relocation model on MIPS at the present time.");
569 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
575 MBB.addLiveIn(Mips::COP013);
576 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
577 .addReg(Mips::COP013)
581 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
582 .addReg(Mips::K0)
589 MBB.addLiveIn(Mips::COP014);
590 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
591 .addReg(Mips::COP014)
595 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
600 MBB.addLiveIn(Mips::COP012);
601 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
602 .addReg(Mips::COP012)
606 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
614 unsigned SrcReg = Mips::ZERO;
619 SrcReg = Mips::K0;
635 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
639 .addReg(Mips::K1)
643 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
644 .addReg(Mips::ZERO)
647 .addReg(Mips::K1)
652 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
653 .addReg(Mips::ZERO)
656 .addReg(Mips::K1)
660 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
661 .addReg(Mips::K1)
698 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
733 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
736 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
737 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
740 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
743 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
744 .addReg(Mips::K1)
748 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
751 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
752 .addReg(Mips::K1)
787 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
794 bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
795 Reg == Mips::HI0 || Reg == Mips::HI0_64);
802 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
803 Reg = Mips::K0;
805 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
806 Reg = Mips::K0_64;
808 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
849 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
872 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
886 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
