Lines Matching defs:Mask
564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
566 if (!Mask)
569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
572 return SDValue(); // Mask+1 is not a power of 2
660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
686 APInt Mask, InvMask;
688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
692 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
697 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
700 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
706 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
707 // thing again using this mask.
709 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
714 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
717 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
770 if (Mask.isAllOnesValue())
772 else if (Mask == 0)
1592 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1595 DAG.getConstant(Mask, DL, VecTy, true),
1605 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1608 DAG.getConstant(Mask, DL, VecTy, true),
1652 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1657 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
2425 // It is therefore possible to lower into SHF when the mask takes the form:
2458 // If the mask has an undef, replace it with the current index.
2463 // Check that non-undef values are the same as in the mask. If they
2512 // It is a SPLATI when the mask is:
2516 // When undef's appear in the mask they are treated as if they were whatever
2539 // It is possible to lower into ILVEV when the mask consists of two of the
2548 // When undef's appear in the mask they are treated as if they were whatever
2585 // It is possible to lower into ILVOD when the mask consists of two of the
2594 // When undef's appear in the mask they are treated as if they were whatever
2632 // It is possible to lower into ILVR when the mask consists of two of the
2641 // When undef's appear in the mask they are treated as if they were whatever
2679 // It is possible to lower into ILVL when the mask consists of two of the
2688 // When undef's appear in the mask they are treated as if they were whatever
2727 // It is possible to lower into PCKEV when the mask consists of two of the
2736 // When undef's appear in the mask they are treated as if they were whatever
2770 // It is possible to lower into PCKOD when the mask consists of two of the
2779 // When undef's appear in the mask they are treated as if they were whatever
2854 llvm_unreachable("shuffle vector mask references neither vector operand?");
