Lines Matching refs:Mips
28 : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B
29 : Mips::J),
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
87 if (Mips::GPR32RegClass.contains(SrcReg)) {
89 Opc = Mips::MOVE16_MM;
91 Opc = Mips::OR, ZeroReg = Mips::ZERO;
92 } else if (Mips::CCRRegClass.contains(SrcReg))
93 Opc = Mips::CFC1;
94 else if (Mips::FGR32RegClass.contains(SrcReg))
95 Opc = Mips::MFC1;
96 else if (Mips::HI32RegClass.contains(SrcReg)) {
97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
99 } else if (Mips::LO32RegClass.contains(SrcReg)) {
100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
102 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
103 Opc = Mips::MFHI_DSP;
104 else if (Mips::LO32DSPRegClass.contains(SrcReg))
105 Opc = Mips::MFLO_DSP;
106 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
111 else if (Mips::MSACtrlRegClass.contains(SrcReg))
112 Opc = Mips::CFCMSA;
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115 if (Mips::CCRRegClass.contains(DestReg))
116 Opc = Mips::CTC1;
117 else if (Mips::FGR32RegClass.contains(DestReg))
118 Opc = Mips::MTC1;
119 else if (Mips::HI32RegClass.contains(DestReg))
120 Opc = Mips::MTHI, DestReg = 0;
121 else if (Mips::LO32RegClass.contains(DestReg))
122 Opc = Mips::MTLO, DestReg = 0;
123 else if (Mips::HI32DSPRegClass.contains(DestReg))
124 Opc = Mips::MTHI_DSP;
125 else if (Mips::LO32DSPRegClass.contains(DestReg))
126 Opc = Mips::MTLO_DSP;
127 else if (Mips::DSPCCRegClass.contains(DestReg)) {
128 BuildMI(MBB, I, DL, get(Mips::WRDSP))
133 else if (Mips::MSACtrlRegClass.contains(DestReg))
134 Opc = Mips::CTCMSA;
136 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
137 Opc = Mips::FMOV_S;
138 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
139 Opc = Mips::FMOV_D32;
140 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
141 Opc = Mips::FMOV_D64;
142 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
143 if (Mips::GPR64RegClass.contains(SrcReg))
144 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
145 else if (Mips::HI64RegClass.contains(SrcReg))
146 Opc = Mips::MFHI64, SrcReg = 0;
147 else if (Mips::LO64RegClass.contains(SrcReg))
148 Opc = Mips::MFLO64, SrcReg = 0;
149 else if (Mips::FGR64RegClass.contains(SrcReg))
150 Opc = Mips::DMFC1;
152 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
153 if (Mips::HI64RegClass.contains(DestReg))
154 Opc = Mips::MTHI64, DestReg = 0;
155 else if (Mips::LO64RegClass.contains(DestReg))
156 Opc = Mips::MTLO64, DestReg = 0;
157 else if (Mips::FGR64RegClass.contains(DestReg))
158 Opc = Mips::DMTC1;
160 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
161 if (Mips::MSA128BRegClass.contains(SrcReg))
162 Opc = Mips::MOVE_V;
189 if (Mips::GPR32RegClass.hasSubClassEq(RC))
190 Opc = Mips::SW;
191 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
192 Opc = Mips::SD;
193 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
194 Opc = Mips::STORE_ACC64;
195 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
196 Opc = Mips::STORE_ACC64DSP;
197 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
198 Opc = Mips::STORE_ACC128;
199 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
200 Opc = Mips::STORE_CCOND_DSP;
201 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
202 Opc = Mips::SWC1;
203 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
204 Opc = Mips::SDC1;
205 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
206 Opc = Mips::SDC164;
208 Opc = Mips::ST_B;
210 Opc = Mips::ST_H;
212 Opc = Mips::ST_W;
214 Opc = Mips::ST_D;
215 else if (Mips::LO32RegClass.hasSubClassEq(RC))
216 Opc = Mips::SW;
217 else if (Mips::LO64RegClass.hasSubClassEq(RC))
218 Opc = Mips::SD;
219 else if (Mips::HI32RegClass.hasSubClassEq(RC))
220 Opc = Mips::SW;
221 else if (Mips::HI64RegClass.hasSubClassEq(RC))
222 Opc = Mips::SD;
228 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
229 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
230 SrcReg = Mips::K0;
231 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
232 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
233 SrcReg = Mips::K0_64;
234 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
235 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
236 SrcReg = Mips::K0;
237 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
238 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
239 SrcReg = Mips::K0_64;
259 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
260 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
262 if (Mips::GPR32RegClass.hasSubClassEq(RC))
263 Opc = Mips::LW;
264 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
265 Opc = Mips::LD;
266 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
267 Opc = Mips::LOAD_ACC64;
268 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
269 Opc = Mips::LOAD_ACC64DSP;
270 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
271 Opc = Mips::LOAD_ACC128;
272 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
273 Opc = Mips::LOAD_CCOND_DSP;
274 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
275 Opc = Mips::LWC1;
276 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
277 Opc = Mips::LDC1;
278 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
279 Opc = Mips::LDC164;
281 Opc = Mips::LD_B;
283 Opc = Mips::LD_H;
285 Opc = Mips::LD_W;
287 Opc = Mips::LD_D;
288 else if (Mips::HI32RegClass.hasSubClassEq(RC))
289 Opc = Mips::LW;
290 else if (Mips::HI64RegClass.hasSubClassEq(RC))
291 Opc = Mips::LD;
292 else if (Mips::LO32RegClass.hasSubClassEq(RC))
293 Opc = Mips::LW;
294 else if (Mips::LO64RegClass.hasSubClassEq(RC))
295 Opc = Mips::LD;
307 unsigned Reg = Mips::K0;
308 unsigned LdOp = Mips::MTLO;
309 if (DestReg == Mips::HI0)
310 LdOp = Mips::MTHI;
313 Reg = Mips::K0_64;
314 if (DestReg == Mips::HI0_64)
315 LdOp = Mips::MTHI64;
317 LdOp = Mips::MTLO64;
336 case Mips::RetRA:
339 case Mips::ERet:
342 case Mips::PseudoMFHI:
343 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
346 case Mips::PseudoMFLO:
347 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
350 case Mips::PseudoMFHI64:
351 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
353 case Mips::PseudoMFLO64:
354 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
356 case Mips::PseudoMTLOHI:
357 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
359 case Mips::PseudoMTLOHI64:
360 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
362 case Mips::PseudoMTLOHI_DSP:
363 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
365 case Mips::PseudoCVT_S_W:
366 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
368 case Mips::PseudoCVT_D32_W:
369 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
371 case Mips::PseudoCVT_S_L:
372 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
374 case Mips::PseudoCVT_D64_W:
375 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
377 case Mips::PseudoCVT_D64_L:
378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
380 case Mips::BuildPairF64:
383 case Mips::BuildPairF64_64:
386 case Mips::ExtractElementF64:
389 case Mips::ExtractElementF64_64:
392 case Mips::MIPSeh_return32:
393 case Mips::MIPSeh_return64:
407 case Mips::BEQ: return Mips::BNE;
408 case Mips::BNE: return Mips::BEQ;
409 case Mips::BGTZ: return Mips::BLEZ;
410 case Mips::BGEZ: return Mips::BLTZ;
411 case Mips::BLTZ: return Mips::BGEZ;
412 case Mips::BLEZ: return Mips::BGTZ;
413 case Mips::BEQ64: return Mips::BNE64;
414 case Mips::BNE64: return Mips::BEQ64;
415 case Mips::BGTZ64: return Mips::BLEZ64;
416 case Mips::BGEZ64: return Mips::BLTZ64;
417 case Mips::BLTZ64: return Mips::BGEZ64;
418 case Mips::BLEZ64: return Mips::BGTZ64;
419 case Mips::BC1T: return Mips::BC1F;
420 case Mips::BC1F: return Mips::BC1T;
421 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
422 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
456 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
457 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
459 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
491 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
492 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
493 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
494 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
495 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
496 Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM) ?
503 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
504 .addReg(Mips::RA_64);
506 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
511 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
552 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
553 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
577 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
580 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
595 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
598 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
606 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
619 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
622 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
630 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
649 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
657 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
672 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
678 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
689 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
690 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
691 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
692 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
