Lines Matching full:case
61 case MVT::v2i1:
62 case MVT::v4i1:
63 case MVT::v2i8:
64 case MVT::v4i8:
65 case MVT::v2i16:
66 case MVT::v4i16:
67 case MVT::v2i32:
68 case MVT::v4i32:
69 case MVT::v2i64:
70 case MVT::v2f32:
71 case MVT::v4f32:
72 case MVT::v2f64:
291 case NVPTXISD::FIRST_NUMBER:
293 case NVPTXISD::CALL:
295 case NVPTXISD::RET_FLAG:
297 case NVPTXISD::LOAD_PARAM:
299 case NVPTXISD::Wrapper:
301 case NVPTXISD::DeclareParam:
303 case NVPTXISD::DeclareScalarParam:
305 case NVPTXISD::DeclareRet:
307 case NVPTXISD::DeclareScalarRet:
309 case NVPTXISD::DeclareRetParam:
311 case NVPTXISD::PrintCall:
313 case NVPTXISD::PrintCallUni:
315 case NVPTXISD::LoadParam:
317 case NVPTXISD::LoadParamV2:
319 case NVPTXISD::LoadParamV4:
321 case NVPTXISD::StoreParam:
323 case NVPTXISD::StoreParamV2:
325 case NVPTXISD::StoreParamV4:
327 case NVPTXISD::StoreParamS32:
329 case NVPTXISD::StoreParamU32:
331 case NVPTXISD::CallArgBegin:
333 case NVPTXISD::CallArg:
335 case NVPTXISD::LastCallArg:
337 case NVPTXISD::CallArgEnd:
339 case NVPTXISD::CallVoid:
341 case NVPTXISD::CallVal:
343 case NVPTXISD::CallSymbol:
345 case NVPTXISD::Prototype:
347 case NVPTXISD::MoveParam:
349 case NVPTXISD::StoreRetval:
351 case NVPTXISD::StoreRetvalV2:
353 case NVPTXISD::StoreRetvalV4:
355 case NVPTXISD::PseudoUseParam:
357 case NVPTXISD::RETURN:
359 case NVPTXISD::CallSeqBegin:
361 case NVPTXISD::CallSeqEnd:
363 case NVPTXISD::CallPrototype:
365 case NVPTXISD::LoadV2:
367 case NVPTXISD::LoadV4:
369 case NVPTXISD::LDGV2:
371 case NVPTXISD::LDGV4:
373 case NVPTXISD::LDUV2:
375 case NVPTXISD::LDUV4:
377 case NVPTXISD::StoreV2:
379 case NVPTXISD::StoreV4:
381 case NVPTXISD::FUN_SHFL_CLAMP:
383 case NVPTXISD::FUN_SHFR_CLAMP:
385 case NVPTXISD::IMAD:
387 case NVPTXISD::Dummy:
389 case NVPTXISD::MUL_WIDE_SIGNED:
391 case NVPTXISD::MUL_WIDE_UNSIGNED:
393 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
394 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
395 case NVPTXISD::Tex1DFloatFloatLevel:
397 case NVPTXISD::Tex1DFloatFloatGrad:
399 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
400 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
401 case NVPTXISD::Tex1DS32FloatLevel:
403 case NVPTXISD::Tex1DS32FloatGrad:
405 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
406 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
407 case NVPTXISD::Tex1DU32FloatLevel:
409 case NVPTXISD::Tex1DU32FloatGrad:
411 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
412 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
413 case NVPTXISD::Tex1DArrayFloatFloatLevel:
415 case NVPTXISD::Tex1DArrayFloatFloatGrad:
417 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
418 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
419 case NVPTXISD::Tex1DArrayS32FloatLevel:
421 case NVPTXISD::Tex1DArrayS32FloatGrad:
423 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
424 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
425 case NVPTXISD::Tex1DArrayU32FloatLevel:
427 case NVPTXISD::Tex1DArrayU32FloatGrad:
429 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
430 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
431 case NVPTXISD::Tex2DFloatFloatLevel:
433 case NVPTXISD::Tex2DFloatFloatGrad:
435 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
436 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
437 case NVPTXISD::Tex2DS32FloatLevel:
439 case NVPTXISD::Tex2DS32FloatGrad:
441 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
442 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
443 case NVPTXISD::Tex2DU32FloatLevel:
445 case NVPTXISD::Tex2DU32FloatGrad:
447 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
448 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
449 case NVPTXISD::Tex2DArrayFloatFloatLevel:
451 case NVPTXISD::Tex2DArrayFloatFloatGrad:
453 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
454 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
455 case NVPTXISD::Tex2DArrayS32FloatLevel:
457 case NVPTXISD::Tex2DArrayS32FloatGrad:
459 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
460 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
461 case NVPTXISD::Tex2DArrayU32FloatLevel:
463 case NVPTXISD::Tex2DArrayU32FloatGrad:
465 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
466 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
467 case NVPTXISD::Tex3DFloatFloatLevel:
469 case NVPTXISD::Tex3DFloatFloatGrad:
471 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
472 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
473 case NVPTXISD::Tex3DS32FloatLevel:
475 case NVPTXISD::Tex3DS32FloatGrad:
477 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
478 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
479 case NVPTXISD::Tex3DU32FloatLevel:
481 case NVPTXISD::Tex3DU32FloatGrad:
483 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
484 case NVPTXISD::TexCubeFloatFloatLevel:
486 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
487 case NVPTXISD::TexCubeS32FloatLevel:
489 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
490 case NVPTXISD::TexCubeU32FloatLevel:
492 case NVPTXISD::TexCubeArrayFloatFloat:
494 case NVPTXISD::TexCubeArrayFloatFloatLevel:
496 case NVPTXISD::TexCubeArrayS32Float:
498 case NVPTXISD::TexCubeArrayS32FloatLevel:
500 case NVPTXISD::TexCubeArrayU32Float:
502 case NVPTXISD::TexCubeArrayU32FloatLevel:
504 case NVPTXISD::Tld4R2DFloatFloat:
506 case NVPTXISD::Tld4G2DFloatFloat:
508 case NVPTXISD::Tld4B2DFloatFloat:
510 case NVPTXISD::Tld4A2DFloatFloat:
512 case NVPTXISD::Tld4R2DS64Float:
514 case NVPTXISD::Tld4G2DS64Float:
516 case NVPTXISD::Tld4B2DS64Float:
518 case NVPTXISD::Tld4A2DS64Float:
520 case NVPTXISD::Tld4R2DU64Float:
522 case NVPTXISD::Tld4G2DU64Float:
524 case NVPTXISD::Tld4B2DU64Float:
526 case NVPTXISD::Tld4A2DU64Float:
529 case NVPTXISD::TexUnified1DFloatS32:
531 case NVPTXISD::TexUnified1DFloatFloat:
533 case NVPTXISD::TexUnified1DFloatFloatLevel:
535 case NVPTXISD::TexUnified1DFloatFloatGrad:
537 case NVPTXISD::TexUnified1DS32S32:
539 case NVPTXISD::TexUnified1DS32Float:
541 case NVPTXISD::TexUnified1DS32FloatLevel:
543 case NVPTXISD::TexUnified1DS32FloatGrad:
545 case NVPTXISD::TexUnified1DU32S32:
547 case NVPTXISD::TexUnified1DU32Float:
549 case NVPTXISD::TexUnified1DU32FloatLevel:
551 case NVPTXISD::TexUnified1DU32FloatGrad:
553 case NVPTXISD::TexUnified1DArrayFloatS32:
555 case NVPTXISD::TexUnified1DArrayFloatFloat:
557 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
559 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
561 case NVPTXISD::TexUnified1DArrayS32S32:
563 case NVPTXISD::TexUnified1DArrayS32Float:
565 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
567 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
569 case NVPTXISD::TexUnified1DArrayU32S32:
571 case NVPTXISD::TexUnified1DArrayU32Float:
573 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
575 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
577 case NVPTXISD::TexUnified2DFloatS32:
579 case NVPTXISD::TexUnified2DFloatFloat:
581 case NVPTXISD::TexUnified2DFloatFloatLevel:
583 case NVPTXISD::TexUnified2DFloatFloatGrad:
585 case NVPTXISD::TexUnified2DS32S32:
587 case NVPTXISD::TexUnified2DS32Float:
589 case NVPTXISD::TexUnified2DS32FloatLevel:
591 case NVPTXISD::TexUnified2DS32FloatGrad:
593 case NVPTXISD::TexUnified2DU32S32:
595 case NVPTXISD::TexUnified2DU32Float:
597 case NVPTXISD::TexUnified2DU32FloatLevel:
599 case NVPTXISD::TexUnified2DU32FloatGrad:
601 case NVPTXISD::TexUnified2DArrayFloatS32:
603 case NVPTXISD::TexUnified2DArrayFloatFloat:
605 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
607 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
609 case NVPTXISD::TexUnified2DArrayS32S32:
611 case NVPTXISD::TexUnified2DArrayS32Float:
613 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
615 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
617 case NVPTXISD::TexUnified2DArrayU32S32:
619 case NVPTXISD::TexUnified2DArrayU32Float:
621 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
623 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
625 case NVPTXISD::TexUnified3DFloatS32:
627 case NVPTXISD::TexUnified3DFloatFloat:
629 case NVPTXISD::TexUnified3DFloatFloatLevel:
631 case NVPTXISD::TexUnified3DFloatFloatGrad:
633 case NVPTXISD::TexUnified3DS32S32:
635 case NVPTXISD::TexUnified3DS32Float:
637 case NVPTXISD::TexUnified3DS32FloatLevel:
639 case NVPTXISD::TexUnified3DS32FloatGrad:
641 case NVPTXISD::TexUnified3DU32S32:
643 case NVPTXISD::TexUnified3DU32Float:
645 case NVPTXISD::TexUnified3DU32FloatLevel:
647 case NVPTXISD::TexUnified3DU32FloatGrad:
649 case NVPTXISD::TexUnifiedCubeFloatFloat:
651 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
653 case NVPTXISD::TexUnifiedCubeS32Float:
655 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
657 case NVPTXISD::TexUnifiedCubeU32Float:
659 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
661 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
663 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
665 case NVPTXISD::TexUnifiedCubeArrayS32Float:
667 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
669 case NVPTXISD::TexUnifiedCubeArrayU32Float:
671 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
673 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
675 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
677 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
679 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
681 case NVPTXISD::Tld4UnifiedR2DS64Float:
683 case NVPTXISD::Tld4UnifiedG2DS64Float:
685 case NVPTXISD::Tld4UnifiedB2DS64Float:
687 case NVPTXISD::Tld4UnifiedA2DS64Float:
689 case NVPTXISD::Tld4UnifiedR2DU64Float:
691 case NVPTXISD::Tld4UnifiedG2DU64Float:
693 case NVPTXISD::Tld4UnifiedB2DU64Float:
695 case NVPTXISD::Tld4UnifiedA2DU64Float:
698 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
699 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
700 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
701 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
702 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
703 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
704 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
705 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
706 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
707 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
708 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
710 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
711 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
712 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
713 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
714 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
715 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
716 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
717 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
718 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
719 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
720 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
722 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
723 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
724 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
725 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
726 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
727 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
728 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
729 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
730 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
731 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
732 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
734 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
735 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
736 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
737 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
738 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
739 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
740 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
741 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
742 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
743 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
744 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
746 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
747 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
748 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
749 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
750 case
751 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
752 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
753 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
754 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
755 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
756 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
758 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
759 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
760 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
761 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
762 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
763 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
764 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
765 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
766 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
767 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
768 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
770 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
771 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
772 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
773 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
774 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
775 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
776 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
777 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
778 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
779 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
780 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
782 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
783 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
784 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
785 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
786 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
787 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
788 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
789 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
790 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
791 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
792 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
794 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
795 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
796 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
797 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
798 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
799 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
800 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
801 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
802 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
803 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
804 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
806 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
807 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
808 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
809 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
810 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
811 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
812 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
813 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
814 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
815 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
816 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
818 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
819 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
820 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
821 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
822 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
823 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
824 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
825 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
826 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
827 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
828 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
830 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
831 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
832 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
833 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
834 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
835 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
836 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
837 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
838 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
839 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
840 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
842 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
843 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
844 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
845 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
846 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
847 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
848 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
849 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
850 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
851 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
852 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
854 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
855 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
856 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
857 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
858 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
859 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
860 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
861 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
862 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
863 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
864 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
866 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
867 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
868 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
869 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
870 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
871 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
872 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
873 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
874 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
875 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
876 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
1415 // This is indirect function call case : PTX requires a prototype of the
1812 case ISD::RETURNADDR:
1814 case ISD::FRAMEADDR:
1816 case ISD::GlobalAddress:
1818 case ISD::INTRINSIC_W_CHAIN:
1820 case ISD::BUILD_VECTOR:
1821 case ISD::EXTRACT_SUBVECTOR:
1823 case ISD::CONCAT_VECTORS:
1825 case ISD::STORE:
1827 case ISD::LOAD:
1829 case ISD::SHL_PARTS:
1831 case ISD::SRA_PARTS:
1832 case ISD::SRL_PARTS:
1834 case ISD::SELECT:
1913 case MVT::v2i8:
1914 case MVT::v2i16:
1915 case MVT::v2i32:
1916 case MVT::v2i64:
1917 case MVT::v2f32:
1918 case MVT::v2f64:
1919 case MVT::v4i8:
1920 case MVT::v4i16:
1921 case MVT::v4i32:
1922 case MVT::v4f32:
1956 case 2:
1959 case 4: {
2342 // We treat this case as if the arg list is empty.
2541 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2543 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2545 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2547 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2549 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2551 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2553 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2555 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2557 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2559 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2561 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2563 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2566 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2568 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2570 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2572 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2574 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2576 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2578 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2580 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2582 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2584 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2586 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2588 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2591 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2593 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2595 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2597 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2599 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2601 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2603 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2605 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2607 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2609 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2611 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2613 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2616 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2618 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2620 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2622 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2624 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2626 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2628 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2630 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2632 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2634 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2636 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2638 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2641 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2643 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2645 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2647 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2649 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2651 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2653 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2655 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2657 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2659 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2661 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2663 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2666 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2668 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2670 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2672 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2674 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2676 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2679 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2681 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2683 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2685 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2687 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2689 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2692 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2694 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2696 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2698 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2700 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2702 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2704 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2706 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2708 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2710 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2712 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2714 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2717 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2719 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2721 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2723 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2725 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2727 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2729 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2731 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2733 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2735 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2737 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2739 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2742 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2744 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2746 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2748 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2750 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2752 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2754 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2756 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2758 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2760 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2762 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2764 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2767 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2769 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2771 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2773 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2775 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2777 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2779 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2781 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2783 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2785 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2787 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2789 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2792 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2794 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2796 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2798 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2800 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2802 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2804 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2806 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2808 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2810 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2812 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2814 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2817 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2819 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2821 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2823 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2825 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2827 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2829 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2831 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2833 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2835 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2837 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2839 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2842 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2844 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2846 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2848 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2850 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2852 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2855 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2857 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2859 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2861 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2863 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2865 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2868 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2870 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2872 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2874 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2876 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2878 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2880 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2882 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2884 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2886 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2888 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2890 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2899 case Intrinsic::nvvm_suld_1d_i8_clamp:
2901 case Intrinsic::nvvm_suld_1d_i16_clamp:
2903 case Intrinsic::nvvm_suld_1d_i32_clamp:
2905 case Intrinsic::nvvm_suld_1d_i64_clamp:
2907 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2909 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2911 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2913 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2915 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2917 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2919 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2921 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2923 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2925 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2927 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2929 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2931 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2933 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2935 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2937 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2939 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2941 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2943 case Intrinsic::nvvm_suld_2d_i8_clamp:
2945 case Intrinsic::nvvm_suld_2d_i16_clamp:
2947 case Intrinsic::nvvm_suld_2d_i32_clamp:
2949 case Intrinsic::nvvm_suld_2d_i64_clamp:
2951 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2953 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2955 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2957 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2959 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2961 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2963 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2965 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2967 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2969 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
2971 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
2973 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
2975 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
2977 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
2979 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
2981 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
2983 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
2985 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
2987 case Intrinsic::nvvm_suld_3d_i8_clamp:
2989 case Intrinsic::nvvm_suld_3d_i16_clamp:
2991 case Intrinsic::nvvm_suld_3d_i32_clamp:
2993 case Intrinsic::nvvm_suld_3d_i64_clamp:
2995 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
2997 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
2999 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3001 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3003 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3005 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3007 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3009 case Intrinsic::nvvm_suld_1d_i8_trap:
3011 case Intrinsic::nvvm_suld_1d_i16_trap:
3013 case Intrinsic::nvvm_suld_1d_i32_trap:
3015 case Intrinsic::nvvm_suld_1d_i64_trap:
3017 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3019 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3021 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3023 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3025 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3027 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3029 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3031 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3033 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3035 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3037 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3039 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3041 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3043 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3045 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3047 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3049 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3051 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3053 case Intrinsic::nvvm_suld_2d_i8_trap:
3055 case Intrinsic::nvvm_suld_2d_i16_trap:
3057 case Intrinsic::nvvm_suld_2d_i32_trap:
3059 case Intrinsic::nvvm_suld_2d_i64_trap:
3061 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3063 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3065 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3067 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3069 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3071 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3073 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3075 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3077 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3079 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3081 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3083 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3085 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3087 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3089 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3091 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3093 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3095 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3097 case Intrinsic::nvvm_suld_3d_i8_trap:
3099 case Intrinsic::nvvm_suld_3d_i16_trap:
3101 case Intrinsic::nvvm_suld_3d_i32_trap:
3103 case Intrinsic::nvvm_suld_3d_i64_trap:
3105 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3107 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3109 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3111 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3113 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3115 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3117 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3119 case Intrinsic::nvvm_suld_1d_i8_zero:
3121 case Intrinsic::nvvm_suld_1d_i16_zero:
3123 case Intrinsic::nvvm_suld_1d_i32_zero:
3125 case Intrinsic::nvvm_suld_1d_i64_zero:
3127 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3129 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3131 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3133 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3135 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3137 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3139 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3141 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3143 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3145 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3147 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3149 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3151 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3153 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3155 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3157 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3159 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3161 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3163 case Intrinsic::nvvm_suld_2d_i8_zero:
3165 case Intrinsic::nvvm_suld_2d_i16_zero:
3167 case Intrinsic::nvvm_suld_2d_i32_zero:
3169 case Intrinsic::nvvm_suld_2d_i64_zero:
3171 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3173 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3175 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3177 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3179 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3181 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3183 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3185 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3187 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3189 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3191 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3193 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3195 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3197 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3199 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3201 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3203 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3205 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3207 case Intrinsic::nvvm_suld_3d_i8_zero:
3209 case Intrinsic::nvvm_suld_3d_i16_zero:
3211 case Intrinsic::nvvm_suld_3d_i32_zero:
3213 case Intrinsic::nvvm_suld_3d_i64_zero:
3215 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3217 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3219 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3221 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3223 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3225 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3227 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3243 case Intrinsic::nvvm_atomic_load_add_f32:
3254 case Intrinsic::nvvm_atomic_load_inc_32:
3255 case Intrinsic::nvvm_atomic_load_dec_32:
3266 case Intrinsic::nvvm_ldu_global_i:
3267 case Intrinsic::nvvm_ldu_global_f:
3268 case Intrinsic::nvvm_ldu_global_p: {
3286 case Intrinsic::nvvm_ldg_global_i:
3287 case Intrinsic::nvvm_ldg_global_f:
3288 case Intrinsic::nvvm_ldg_global_p: {
3308 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3309 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3310 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3311 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3312 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3313 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3314 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3315 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3316 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3317 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3318 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3319 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3320 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3321 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3322 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3323 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3324 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3325 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3326 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3327 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3328 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3329 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3330 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3331 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3332 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3333 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3334 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3335 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3336 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3337 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3338 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3339 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3340 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3341 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3342 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3343 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3344 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3345 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3346 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3347 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3348 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3349 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3350 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3351 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3352 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3353 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3354 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3355 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3356 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3357 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3358 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3359 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3360 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3361 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3362 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3363 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3374 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3375 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3376 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3377 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3378 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3379 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3380 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3381 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3382 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3383 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3384 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3385 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3386 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3387 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3388 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3389 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3390 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3391 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3392 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3393 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3394 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3395 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3396 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3397 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3398 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3399 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3400 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3401 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3402 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3403 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3404 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3405 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3406 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3407 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3408 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3409 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3410 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3411 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3412 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3413 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3414 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3415 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3416 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3417 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3418 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3419 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3420 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3421 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3422 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3423 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3424 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3425 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3426 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3427 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3428 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3429 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3430 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3431 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3432 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3433 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3434 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3435 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3436 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3437 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3438 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3439 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3440 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3441 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3442 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3443 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3444 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3445 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3446 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3447 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3448 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3449 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3450 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3451 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3452 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3453 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3454 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3455 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3456 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3457 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3458 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3459 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3460 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3461 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3462 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3463 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3464 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3465 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3466 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3467 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3468 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3469 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3470 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3471 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3472 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3473 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3474 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3475 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3476 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3477 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3478 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3479 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3480 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3481 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3482 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3483 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3484 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3485 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3496 case Intrinsic::nvvm_suld_1d_i8_clamp:
3497 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3498 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3499 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3500 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3501 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3502 case Intrinsic::nvvm_suld_2d_i8_clamp:
3503 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3504 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3505 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3506 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3507 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3508 case Intrinsic::nvvm_suld_3d_i8_clamp:
3509 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3510 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3511 case Intrinsic::nvvm_suld_1d_i8_trap:
3512 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3513 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3514 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3515 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3516 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3517 case Intrinsic::nvvm_suld_2d_i8_trap:
3518 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3519 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3520 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3521 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3522 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3523 case Intrinsic::nvvm_suld_3d_i8_trap:
3524 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3525 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3526 case Intrinsic::nvvm_suld_1d_i8_zero:
3527 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3528 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3529 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3530 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3531 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3532 case Intrinsic::nvvm_suld_2d_i8_zero:
3533 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3534 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3535 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3536 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3537 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3538 case Intrinsic::nvvm_suld_3d_i8_zero:
3539 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3540 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3551 case Intrinsic::nvvm_suld_1d_i16_clamp:
3552 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3553 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3554 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3555 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3556 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3557 case Intrinsic::nvvm_suld_2d_i16_clamp:
3558 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3559 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3560 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3561 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3562 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3563 case Intrinsic::nvvm_suld_3d_i16_clamp:
3564 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3565 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3566 case Intrinsic::nvvm_suld_1d_i16_trap:
3567 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3568 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3569 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3570 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3571 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3572 case Intrinsic::nvvm_suld_2d_i16_trap:
3573 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3574 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3575 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3576 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3577 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3578 case Intrinsic::nvvm_suld_3d_i16_trap:
3579 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3580 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3581 case Intrinsic::nvvm_suld_1d_i16_zero:
3582 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3583 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3584 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3585 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3586 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3587 case Intrinsic::nvvm_suld_2d_i16_zero:
3588 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3589 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3590 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3591 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3592 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3593 case Intrinsic::nvvm_suld_3d_i16_zero:
3594 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3595 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3606 case Intrinsic::nvvm_suld_1d_i32_clamp:
3607 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3608 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3609 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3610 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3611 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3612 case Intrinsic::nvvm_suld_2d_i32_clamp:
3613 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3614 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3615 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3616 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3617 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3618 case Intrinsic::nvvm_suld_3d_i32_clamp:
3619 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3620 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3621 case Intrinsic::nvvm_suld_1d_i32_trap:
3622 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3623 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3624 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3625 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3626 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3627 case Intrinsic::nvvm_suld_2d_i32_trap:
3628 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3629 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3630 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3631 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3632 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3633 case Intrinsic::nvvm_suld_3d_i32_trap:
3634 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3635 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3636 case Intrinsic::nvvm_suld_1d_i32_zero:
3637 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3638 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3639 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3640 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3641 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3642 case Intrinsic::nvvm_suld_2d_i32_zero:
3643 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3644 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3645 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3646 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3647 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3648 case Intrinsic::nvvm_suld_3d_i32_zero:
3649 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3650 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3661 case Intrinsic::nvvm_suld_1d_i64_clamp:
3662 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3663 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3664 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3665 case Intrinsic::nvvm_suld_2d_i64_clamp:
3666 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3667 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3668 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3669 case Intrinsic::nvvm_suld_3d_i64_clamp:
3670 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3671 case Intrinsic::nvvm_suld_1d_i64_trap:
3672 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3673 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3674 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3675 case Intrinsic::nvvm_suld_2d_i64_trap:
3676 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3677 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3678 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3679 case Intrinsic::nvvm_suld_3d_i64_trap:
3680 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3681 case Intrinsic::nvvm_suld_1d_i64_zero:
3682 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3683 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3684 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3685 case Intrinsic::nvvm_suld_2d_i64_zero:
3686 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3687 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3688 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3689 case Intrinsic::nvvm_suld_3d_i64_zero:
3690 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3728 case 0: // "r", "r+i" or "i" is allowed
3730 case 1:
3754 case 'b':
3755 case 'r':
3756 case 'h':
3757 case 'c':
3758 case 'l':
3759 case 'f':
3760 case 'd':
3761 case '0':
3762 case 'N':
3775 case 'b':
3777 case 'c':
3779 case 'h':
3781 case 'r':
3783 case 'l':
3784 case 'N':
3786 case 'f':
3788 case 'd':
3834 // Skip non-integer, non-scalar case
3999 // We only handle the i8 case
4049 case ISD::SETULT:
4050 case ISD::SETULE:
4051 case ISD::SETLT:
4052 case ISD::SETLE:
4056 case ISD::SETGT:
4057 case ISD::SETGE:
4058 case ISD::SETUGT:
4059 case ISD::SETUGE:
4260 case ISD::ADD:
4261 case ISD::FADD:
4263 case ISD::MUL:
4265 case ISD::SHL:
4267 case ISD::AND:
4269 case ISD::SELECT:
4290 case MVT::v2i8:
4291 case MVT::v2i16:
4292 case MVT::v2i32:
4293 case MVT::v2i64:
4294 case MVT::v2f32:
4295 case MVT::v2f64:
4296 case MVT::v4i8:
4297 case MVT::v4i16:
4298 case MVT::v4i32:
4299 case MVT::v4f32:
4337 case 2:
4341 case 4: {
4388 case Intrinsic::nvvm_ldg_global_i:
4389 case Intrinsic::nvvm_ldg_global_f:
4390 case Intrinsic::nvvm_ldg_global_p:
4391 case Intrinsic::nvvm_ldu_global_i:
4392 case Intrinsic::nvvm_ldu_global_f:
4393 case Intrinsic::nvvm_ldu_global_p: {
4418 case 2:
4422 case Intrinsic::nvvm_ldg_global_i:
4423 case Intrinsic::nvvm_ldg_global_f:
4424 case Intrinsic::nvvm_ldg_global_p:
4427 case Intrinsic::nvvm_ldu_global_i:
4428 case Intrinsic::nvvm_ldu_global_f:
4429 case Intrinsic::nvvm_ldu_global_p:
4435 case 4: {
4439 case Intrinsic::nvvm_ldg_global_i:
4440 case Intrinsic::nvvm_ldg_global_f:
4441 case Intrinsic::nvvm_ldg_global_p:
4444 case Intrinsic::nvvm_ldu_global_i:
4445 case Intrinsic::nvvm_ldu_global_f:
4446 case Intrinsic::nvvm_ldu_global_p:
4520 case ISD::LOAD:
4523 case ISD::INTRINSIC_W_CHAIN:
