Lines Matching refs:addReg
354 .addReg(SrcReg)
358 .addReg(SrcReg, RegState::Kill)
363 .addReg(SrcReg)
367 .addReg(SrcReg, RegState::Kill)
372 .addReg(SrcReg)
376 .addReg(SrcReg, RegState::Kill)
380 .addReg(DstReg, RegState::Kill)
764 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
770 .addReg(FPReg)
772 .addReg(SPReg);
777 .addReg(PPC::R30)
779 .addReg(SPReg);
784 .addReg(BPReg)
786 .addReg(SPReg);
791 .addReg(ScratchReg)
793 .addReg(SPReg);
797 .addReg(TempReg, getKillRegState(true))
799 .addReg(SPReg);
810 .addReg(SPReg)
811 .addReg(SPReg);
817 .addReg(SPReg)
822 .addReg(SPReg)
828 .addReg(ScratchReg, RegState::Kill)
834 .addReg(TempReg, RegState::Kill)
837 .addReg(ScratchReg, RegState::Kill)
838 .addReg(TempReg, RegState::Kill);
841 .addReg(SPReg, RegState::Kill)
842 .addReg(SPReg)
843 .addReg(ScratchReg);
847 .addReg(SPReg)
849 .addReg(SPReg);
855 .addReg(ScratchReg, RegState::Kill)
858 .addReg(SPReg, RegState::Kill)
859 .addReg(SPReg)
860 .addReg(ScratchReg);
923 .addReg(SPReg)
924 .addReg(SPReg);
1110 .addReg(FPReg).addImm(FrameSize);
1115 .addReg(ScratchReg, RegState::Kill)
1118 .addReg(SPReg)
1119 .addReg(FPReg)
1120 .addReg(ScratchReg);
1124 .addReg(SPReg)
1129 .addReg(SPReg);
1136 .addReg(SPReg);
1144 .addReg(SPReg);
1149 .addReg(SPReg);
1154 .addReg(PPC::R30)
1156 .addReg(SPReg);
1161 .addReg(SPReg);
1166 .addReg(TempReg, getKillRegState(i == e-1));
1169 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1183 .addReg(SPReg).addImm(CallerAllocatedAmt);
1188 .addReg(ScratchReg, RegState::Kill)
1191 .addReg(SPReg)
1192 .addReg(FPReg)
1193 .addReg(ScratchReg);
1580 CRMIB.addReg(Reg, RegState::ImplicitKill);
1597 .addReg(Reg, RegState::ImplicitKill);
1601 .addReg(PPC::R12,
1639 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1643 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1647 .addReg(MoveReg, getKillRegState(true)));
1671 .addReg(StackReg, RegState::Kill)
1678 .addReg(TmpReg, RegState::Kill)
1681 .addReg(StackReg, RegState::Kill)
1682 .addReg(TmpReg);
