Lines Matching defs:is64bit
2013 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2015 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2016 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2120 bool is64bit = Subtarget.isPPC64();
2131 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2132 is64bit ? MVT::i64 : MVT::i32);
2142 if (is64bit) {
2157 if (is64bit) {
2175 if (is64bit) {
8220 bool is64bit = Subtarget.isPPC64();
8221 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8242 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8284 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8291 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8293 if (is64bit)
8316 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8318 BuildMI(BB, dl, TII->get(is64bit
8320 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8843 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8907 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8936 bool is64bit = Subtarget.isPPC64();
8959 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8976 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
9011 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
9018 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
9020 if (is64bit)
11178 bool is64Bit = isPPC64 && VT == MVT::i64;
11180 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11183 (is64Bit ? PPC::X13 : PPC::R13))
