Lines Matching refs:Const
57 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
58 const PPCSubtarget &STI)
974 const DataLayout &DL) const {
987 bool PPCTargetLowering::useSoftFloat() const {
991 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1082 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1083 EVT VT) const {
1093 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1109 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1197 const PPCSubtarget& Subtarget =
1198 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1657 SelectionDAG &DAG) const {
1743 bool Aligned) const {
1841 SelectionDAG &DAG) const {
1870 SelectionDAG &DAG) const {
1955 static bool GetLabelAccessInfo(const TargetMachine &TM,
1956 const PPCSubtarget &Subtarget,
1958 const GlobalValue *GV = nullptr) {
2027 SelectionDAG &DAG) const {
2030 const Constant *C = CP->getConstVal();
2057 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2085 SelectionDAG &DAG) const {
2088 const BlockAddress *BA = BASDN->getBlockAddress();
2107 SelectionDAG &DAG) const {
2118 const GlobalValue *GV = GA->getGlobal();
2121 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2197 SelectionDAG &DAG) const {
2201 const GlobalValue *GV = GSDN->getGlobal();
2237 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2302 const PPCSubtarget &Subtarget) const {
2308 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2410 const PPCSubtarget &Subtarget) const {
2422 SelectionDAG &DAG) const {
2427 SelectionDAG &DAG) const {
2464 const PPCSubtarget &Subtarget) const {
2475 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2524 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2562 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2578 static const MCPhysReg ArgRegs[] = {
2582 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2605 static const MCPhysReg ArgRegs[] = {
2610 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2629 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2634 static const MCPhysReg QFPR[] = {
2757 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2768 const SmallVectorImpl<ISD::InputArg>
2772 const {
2790 const SmallVectorImpl<ISD::InputArg>
2793 SmallVectorImpl<SDValue> &InVals) const {
2850 const TargetRegisterClass *RC;
2946 static const MCPhysReg GPArgRegs[] = {
2950 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2952 static const MCPhysReg FPArgRegs[] = {
3025 SDLoc dl) const {
3040 const SmallVectorImpl<ISD::InputArg>
3043 SmallVectorImpl<SDValue> &InVals) const {
3062 static const MCPhysReg GPR[] = {
3066 static const MCPhysReg VR[] = {
3070 static const MCPhysReg VSRH[] = {
3075 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3076 const unsigned Num_FPR_Regs = 13;
3077 const unsigned Num_VR_Regs = array_lengthof(VR);
3078 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3378 const TargetRegisterClass *RC;
3462 const SmallVectorImpl<ISD::InputArg>
3465 SmallVectorImpl<SDValue> &InVals) const {
3483 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3487 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3491 static const MCPhysReg VR[] = {
3496 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3497 const unsigned Num_FPR_Regs = 13;
3498 const unsigned Num_VR_Regs = array_lengthof( VR);
3502 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3848 const SmallVectorImpl<ISD::InputArg> &Ins,
3849 SelectionDAG& DAG) const {
3911 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3940 const PPCFrameLowering *FL =
3995 SDLoc dl) const {
4106 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4304 bool isLocalCall(const SDValue &Callee)
4314 const SmallVectorImpl<ISD::InputArg> &Ins,
4316 SmallVectorImpl<SDValue> &InVals) const {
4366 const SmallVectorImpl<ISD::InputArg> &Ins,
4368 ImmutableCallSite *CS) const {
4388 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4389 const uint32_t *Mask =
4464 SmallVectorImpl<SDValue> &InVals) const {
4506 const SmallVectorImpl<ISD::OutputArg> &Outs,
4507 const SmallVectorImpl<SDValue> &OutVals,
4508 const SmallVectorImpl<ISD::InputArg> &Ins,
4511 ImmutableCallSite *CS) const {
4731 SDLoc dl) const {
4748 const SmallVectorImpl<ISD::OutputArg> &Outs,
4749 const SmallVectorImpl<SDValue> &OutVals,
4750 const SmallVectorImpl<ISD::InputArg> &Ins,
4753 ImmutableCallSite *CS) const {
4786 static const MCPhysReg GPR[] = {
4790 static const MCPhysReg VR[] = {
4794 static const MCPhysReg VSRH[] = {
4799 const unsigned NumGPRs = array_lengthof(GPR);
4800 const unsigned NumFPRs = 13;
4801 const unsigned NumVRs = array_lengthof(VR);
4802 const unsigned NumQFPRs = NumFPRs;
4996 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4998 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5036 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5037 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5058 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5059 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5378 const SmallVectorImpl<ISD::OutputArg> &Outs,
5379 const SmallVectorImpl<SDValue> &OutVals,
5380 const SmallVectorImpl<ISD::InputArg> &Ins,
5383 ImmutableCallSite *CS) const {
5489 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5493 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5497 static const MCPhysReg VR[] = {
5501 const unsigned NumGPRs = array_lengthof(GPR_32);
5502 const unsigned NumFPRs = 13;
5503 const
5505 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5548 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5550 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5569 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5570 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5769 const SmallVectorImpl<ISD::OutputArg> &Outs,
5770 LLVMContext &Context) const {
5779 const SmallVectorImpl<ISD::OutputArg> &Outs,
5780 const SmallVectorImpl<SDValue> &OutVals,
5781 SDLoc dl, SelectionDAG &DAG) const {
5827 SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const {
5843 const PPCSubtarget &Subtarget) const {
5872 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5895 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5919 const PPCSubtarget &Subtarget) const {
5939 SelectionDAG &DAG) const {
5947 SelectionDAG &DAG) const {
5953 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5978 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
6001 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
6012 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
6116 SDLoc dl) const {
6180 SDLoc dl) const {
6211 SDLoc dl) const {
6234 ISD::LoadExtType ET) const {
6277 SelectionDAG &DAG) const {
6297 SDLoc dl) const {
6325 SelectionDAG &DAG) const {
6576 SelectionDAG &DAG) const {
6639 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6668 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6697 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6736 static const MVT VTys[] = { // canonical VT to use for each size.
6807 SelectionDAG &DAG) const {
7006 static const signed char SplatCsts[] = {
7023 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7034 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7045 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7057 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7170 SelectionDAG &DAG) const {
7357 bool &isDot, const PPCSubtarget &Subtarget) {
7470 SelectionDAG &DAG) const {
7536 SelectionDAG &DAG) const {
7560 SelectionDAG &DAG) const {
7578 SelectionDAG &DAG) const {
7646 SelectionDAG &DAG) const {
7742 SelectionDAG &DAG) const {
7876 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7949 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8013 SelectionDAG &DAG) const {
8101 bool IsLoad) const {
8111 bool IsLoad) const {
8124 unsigned BinOpcode) const {
8126 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8153 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8209 unsigned BinOpcode) const {
8215 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8223 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8242 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8339 MachineBasicBlock *MBB) const {
8341 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8346 const BasicBlock *BB = MBB->getBasicBlock();
8354 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8403 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8404 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8405 const int64_t BPOffset = 4 * PVT.getStoreSize();
8408 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8438 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8486 MachineBasicBlock *MBB) const {
8488 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8501 const TargetRegisterClass *RC =
8517 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8518 const int64_t SPOffset = 2 * PVT.getStoreSize();
8519 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8520 const int64_t BPOffset = 4 * PVT.getStoreSize();
8595 MachineBasicBlock *BB) const {
8620 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8624 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8959 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
9142 static std::string getRecipOp(const char *Base, EVT VT) {
9158 bool &UseOneConstNR) const {
9180 unsigned &RefinementSteps) const {
9199 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9245 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9261 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9262 const GlobalValue *GV1 = nullptr;
9263 const GlobalValue *GV2 = nullptr;
9403 for (const SDUse &O : ChainNext->ops())
9444 DAGCombinerInfo &DCI) const {
9722 DAGCombinerInfo &DCI) const {
10001 DAGCombinerInfo &DCI) const {
10076 DAGCombinerInfo &DCI) const {
10125 DAGCombinerInfo &DCI) const {
10175 DAGCombinerInfo &DCI) const {
10719 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10721 std::vector<SDNode *> *Created) const {
10754 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10757 const SelectionDAG &DAG,
10758 unsigned Depth) const {
10794 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10808 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10833 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10866 AsmOperandInfo &info, const char *constraint) const {
10916 std::pair<unsigned, const TargetRegisterClass *>
10917 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10919 MVT VT) const {
10964 std::pair<unsigned, const TargetRegisterClass *> R =
10993 SelectionDAG &DAG) const {
11066 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11067 const AddrMode &AM, Type *Ty,
11068 unsigned AS) const {
11104 SelectionDAG &DAG) const {
11139 SelectionDAG &DAG) const {
11169 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11170 SelectionDAG &DAG) const {
11192 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11198 const CallInst &I,
11199 unsigned Intrinsic) const {
11404 MachineFunction &MF) const {
11406 const Function *F = MF.getFunction();
11432 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11433 Type *Ty) const {
11442 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11450 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11458 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11478 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11483 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11487 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11494 bool *Fast) const {
11526 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11543 const MCPhysReg *
11544 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11549 static const MCPhysReg ScratchRegs[] = {
11557 const Constant *PersonalityFn) const {
11562 const Constant *PersonalityFn) const {
11568 EVT VT , unsigned DefinedValues) const {
11580 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11590 const TargetLibraryInfo *LibInfo) const {
